Method and apparatus for regulating the output voltage of negative charge pumps

Claim 2

A regulation circuit, comprising: a source of a reference voltage, a charge pump circuit, a first voltage divider circuit connected between an output of the charge pump and the source of reference voltage for furnishing a first voltage, a second voltage divider connected between the source of reference voltage and a known voltage level for furnishing a second voltage, a comparator for comparing the output of the charge pump circuit with the reference voltage, and an oscillator for operating the charge pump when the first voltage is less than the second voltage and for interrupting operation of the charge pump when the first voltage is greater than the second voltage.

Claim 3

A regulation circuit as claimed in claim 1 in which each of the first and second voltage divider circuits includes a diode-connected transistor.

Claim 4

A regulation circuit as claimed in claim 2 in which the comparator is a differential amplifier circuit.

Claim 5

A regulation circuit as claimed in claim 1 in which the charge pump is a negative charge pump.

Claim 6

A regulation circuit as claimed in claim 1 in which the charge pump is a bootstrap charge pump, and the oscillator provides four trains of non-overlapping clock pulses for driving the charge pump.

Claim 7

A computer system, comprising: a central processor; a system bus coupled to the processor; a main memory coupled to the system bus; and a programmable non-volatile long term memory coupled to the system bus, further comprising a flash EEPROM memory array, and a circuit for furnishing voltages for operating the flash EEPROM memory array that further comprises a source of a reference voltage, a charge pump, a first voltage divider circuit connected between an output of the charge pump and the source of reference voltage for furnishing a first voltage, a second voltage divider connected between the source of reference voltage and a known voltage level for furnishing a second voltage, a comparator for comparing the output of the charge pump circuit with the reference voltage, and an oscillator for operating the charge pump when the first voltage is less than the second voltage and for interrupting operation of the charge pump when the first voltage is greater than the second voltage.

Claim 8

A computer system, comprising: a central processor; a system bus coupled to the processor; a main memory coupled to the system bus; and a programmable non-volatile long term memory coupled to the system bus, further comprising a flash EEPROM memory array, and a circuit for furnishing voltages for operating the flash EEPROM memory array that further comprises a source of a reference voltage, a charge pump, a first voltage divider circuit connected between an output of the charge pump and the source of reference voltage for furnishing a first voltage, a second voltage divider connected between the source of reference voltage and a known voltage level for furnishing a second voltage, a comparator for comparing the output of the charge pump circuit with the reference voltage, and an oscillator for operating the charge pump when the first voltage is less than the second voltage and for interrupting operation of the charge pump when the first voltage is greater than the second voltage.

Claim 9

A computer system as claimed in claim 6 in which each of the first and second voltage divider circuits includes a diode-connected transistor.

Claim 10

A computer system as claimed in claim 6 in which the comparator is a differential amplifier circuit.

Claim 11

A computer system as claimed in claim 6 in which the charge pump is a negative charge pump.

Claim 12

A computer system as claimed in claim 6 in which the charge pump is a bootstrap charge pump, and the oscillator provides four trains of non-overlapping clock pulses for driving the charge pump.