Self-time processor with dynamic clock generator having plurality of tracking elements for outputting sequencing signals to functional units

Claim 3

The system of claim 1 and further comprising a single integrated circuit including said tracking element and said functional unit.

Claim 4

The system of claim 1 and further comprising: a second functional unit coupled to said sequencing circuitry for executing a second functional unit operation having a second functional unit operation delay, said second functional unit comprising a second functional unit processing path for executing at least a portion of said second functional unit operation, said portion of said second functional unit operation having a delay at least as great as said second functional unit operation delay, and said second functional unit processing path comprising a plurality of second functional unit processing path components; and a second tracking element coupled to said sequencing circuitry and comprising a second tracking element processing path for executing a second tracking element operation and for outputting a second tracking signal in response to said second tracking element operation, said second tracking element processing path comprising a plurality of second tracking element processing path components duplicating said second functional unit processing path components, wherein said second tracking operation has a delay at least as great as said delay of said portion of said second functional unit operation.

Claim 5

The system of claim 3 wherein said sequencing circuitry inputs said second tracking signal and outputs said sequencing signal in response to at least one of said tracking signals.

Claim 6

The system of claim 4 wherein said functional units output respective select signals, said select signals indicating operations to be executed with said functional units, and said sequencing circuitry selects at least one of said tracking elements for executing a respective tracking element operation in response to said operations indicated by said select signals, so that said sequencing circuitry outputs said sequencing signal in response to at least one said selected tracking element's tracking signal.

Claim 7

The system of claim 1 and further comprising a second functional unit coupled to said sequencing circuitry for executing a second functional unit operation and for outputting a completion signal in response thereto, wherein said sequencing circuitry inputs said completion signal and outputs said sequencing signal in response to said completion signal.

Claim 8

The system of claim 6 wherein said sequencing circuitry delays a transition of said sequencing signal while waiting for said completion signal.

Claim 9

The system of claim 1 wherein said sequencing circuitry outputs said sequencing signal so that a time between transitions of said sequencing signal is substantially equal to said delay of said portion of said functional unit operation.

Claim 10

The system of claim 1 wherein said plurality of tracking element processing path components are arranged relative to one another differently than said plurality of functional unit processing path components.

Claim 11

The system of claim 9 wherein said plurality of functional unit processing path components has a first signal load, and wherein said plurality of tracking element processing path components has a second signal load.

Claim 14

The method of claim 11 and further comprising: executing a second functional unit operation with a second functional unit, said second functional unit operation having a second functional unit operation delay, said second functional unit comprising a second functional unit processing path for executing at least a portion of said second functional unit operation, said portion of said second functional unit operation having a delay at least as great as said second functional unit operation delay, and said second functional unit processing path comprising a plurality of second functional unit processing path components; and executing a second tracking element operation with a second tracking element, said second tracking element comprising a second tracking element processing path for executing said second tracking element operation and for outputting a second tracking signal in response to said second tracking element operation, said second tracking element processing path comprising a plurality of second tracking element processing path components duplicating said second functional unit processing path components, wherein said second tracking operation has a delay at least as great as said delay of said portion of said second functional unit operation.

Claim 15

The method of claim 12 wherein said outputting said sequencing signal comprises inputting said second tracking signal and outputting said sequencing signal in response to at least one of said tracking signals.

Claim 16

The method of claim 13 and further comprising: outputting respective select signals from said functional units, said select signals indicating operations to be executed with said functional units; and selecting at least one of said tracking elements for executing a respective tracking element operation in response to said operations indicated by said select signals, wherein said outputting said sequencing signal comprises outputting said sequencing signal in response to at least one said selected tracking element's tracking signal.

Claim 17

The method of claim 11 and further comprising: executing a second functional unit operation with a second functional unit; and outputting a completion signal in response to said second functional unit operation, wherein said outputting said sequencing signal comprises inputting said completion signal and outputting said sequencing signal in response to said completion signal.

Claim 18

The method of claim 15 wherein said outputting said sequencing signal comprises delaying a transition of said sequencing signal while waiting for said completion signal.

Claim 19

The method of claim 11 wherein said outputting said sequencing signal comprises outputting said sequencing signal so that a time between transitions of said sequencing signal is substantially equal to said delay of said portion of said functional unit operation.

Claim 20

The method of claim 11 wherein said executing said tracking element operation comprises executing said tracking element operation with said tracking element, a single integrated circuit including said tracking element and said functional unit.

Claim 21

The method of claim 11 wherein said executing said tracking element operation comprises executing said tracking element operation with said tracking element, said plurality of tracking element processing path components being arranged relative to one another differently than said plurality of functional unit processing path components.

Claim 22

The method of claim 19 wherein said executing said tracking element operation comprises executing said tracking element operation with said tracking element, said plurality of functional unit processing path components having a first signal load, and said plurality of tracking element processing path components having a second signal load.