Patent US5553104A successfully refreshed from Google Patents.
US5553104A
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Information recording/reproducing apparatus having a clock timing extraction circuit for extracting a clock signal from an input data signal
Assignee: HGST Japan Ltd
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Filing: 1994-06-29
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Granted: 1996-09-03
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Expires: 2014-06-29
Abstract
Abstract A clock timing extraction circuit for use in an information recording/reproducing apparatus has a phase comparator for comparing the reproduced signal with a selected clock signal to generate a phase error signal, a clock signal generation circuit for adjusting frequency to cause the error signal to approach zero according to the phase error signal and outputting a plurality of clock signals having mutually different phase differences, a selection circuit for outputting one of the plurality of clock signals on the basis of a selection signal, a phase difference judgement circuit for determining one of the plurality of clock signals having a minimum phase error (Vdet) and generating a selection signal for selection of the clock signal having the minimum phase difference, and a freeze circuit for blocking an output of the phase comparator until the clock signal having the minimum phase error is selected. The information recording/reproducing apparatus has an AGC circuit for limiting an amplitude of a reproduced signal received from a recording medium, the aforementioned clock timing extraction circuit, and a decoder circuit. The clock timing extraction circuit extracts a clock signal from an output signal of the AGC circuit and the decoder decodes the output signal of the AGC circuit on the basis of the extracted clock signal.
Inventors
- 👤 Terumi Takashi
- 👤 Akihiko Hirano
- 👤 Kazunori Iwabuchi
- 👤 Hideyuki Yamakawa
- 👤 Yoshiteru Ishida
- 👤 Kazuhisa Shiraishi
- 👤 Kazutoshi Ashikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 02:18
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0995; H03L7/0996; G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B27/00; G11B27/10; G11B27/19; G11B27/28; G11B27/30; H03L7/081; H03L7/16; H03L7/18; H03L7/183; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0337
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
167 words
A clock timing extraction circuit for generating a clock signal synchronized with a reproduced signal in an apparatus for recording/reproducing data in/form an information recording medium, comprising: a phase comparator for comparing said reproduced signal with a selected clock signal to generate a phase error signal; a clock signal generation circuit, having an output signal whose frequency is adjusted in order to cause said phase error signal to approach zero, and outputting a plurality of clock signals having mutually different phase differences; a selection circuit for outputting one of said plurality of clock signals as the selected clock signal on the basis of a selection signal; a phase difference judgment circuit for receiving said reproduced signal and for determining one of said plurality of clock signals having a minimum phase error and generating the selection signal for selection of the selected clock signal; and a freeze circuit for blocking an output of said phase comparator until said selected clock signal having the minimum phase error is selected.
Claim 2
Dependent Claim
167 words
A clock timing extraction circuit for generating a clock signal synchronized with a reproduced signal in an apparatus for recording/reproducing data in/form an information recording medium, comprising: a phase comparator for comparing said reproduced signal with a selected clock signal to generate a phase error signal; a clock signal generation circuit, having an output signal whose frequency is adjusted in order to cause said phase error signal to approach zero, and outputting a plurality of clock signals having mutually different phase differences; a selection circuit for outputting one of said plurality of clock signals as the selected clock signal on the basis of a selection signal; a phase difference judgment circuit for receiving said reproduced signal and for determining one of said plurality of clock signals having a minimum phase error and generating the selection signal for selection of the selected clock signal; and a freeze circuit for blocking an output of said phase comparator until said selected clock signal having the minimum phase error is selected.
Claim 3
Dependent Claim
133 words
A clock timing extraction circuit as set for in claim 1, wherein said phase difference judgement circuit generates a first selection signal to select a first clock signal from said plurality of clock signals, judges whether or not the phase error between said reproduced signal and said first clock signal issued from said selection circuit corresponds to a predetermined value, generates the selection signal to maintain said first clock signal when the phase error has the predetermined value and generates the selection signal to select the clock signal corresponding to the predetermined value of the phase error when the phase error does not have the predetermined value; and said freeze circuit blocks the output of said phase comparator until the clock signal corresponding to the predetermined value of the phase error is selected.
Claim 4
Dependent Claim
80 words
A clock timing extraction circuit as set forth in claim 2, wherein the plurality of clock signals output by said clock signal generation circuit are represented by `n` clock signals having phase mutually shifted by 180 degrees (`n`: positive integer), and said phase difference judgement circuit generates the selection signal to select one of said `n` clock signals whose phase error with respect to said reproduced signal has a value included in a range of -180 degrees/n to +180 degrees/n.
Claim 5
Dependent Claim
68 words
A clock timing extracting circuit as set forth in claim 3, wherein said clock signal generation circuit generates two clock signals having phase mutually shifted by 180 degrees, and said phase difference judgement circuit generates the selection signal to select one of said 2 clock signals whose phase error with respect to said reproduced signal has a value included in a range of -90 degrees to +90 degrees.
Claim 6
Dependent Claim
40 words
A clock timing extraction circuit as set forth in claim 2, wherein said phase difference judgement circuit detects the phase error between said selected clock signal and said reproduced signal on said basis of the output of said phase comparator.
Claim 7
Dependent Claim
36 words
A clock timing extraction circuit as set forth in claim 5, wherein said phase comparator generates an output signal which linearly varies in response to variation of said phase error between -180 degrees and 180 degrees.
Claim 8
Dependent Claim
63 words
A clock timing extraction circuit as set forth in claim 2 wherein said clock signal generation circuit includes a clock generator for generating a single original clock signal and a converter for subjecting said original clock signal to a frequency dividing operation to generate `n` clock signals having different frequencies and representing the plurality of clock signals output by the clock generation circuit.
Claim 9
Dependent Claim
191 words
A clock timing extraction circuit for generating a clock signal synchronized with a reproduced signal in an apparatus for recording/reproducing data in/form an information recording medium, comprising: a phase synchronization feedback loop including a phase comparator for comparing said reproduced signal with a selected clock signal to generate a phase error signal and a clock signal generation circuit, having an output signal whose frequency is adjusted in order to cause said phase error signal to approach zero, and for outputting a plurality of clock signals having a phase difference therebetween, said phase comparator having an output characteristic with a plurality of phase error points of synchronization stable points present in one period; a phase difference judgment circuit for receiving the reproduced signal and for detecting a phase error when a phase acquisition operation is completed in said feedback loop on the basis of any one of said plurality of clock signals to generate a selection signal according to said phase error detected by the phase difference judgment circuit; and a selection circuit for outputting one of said plurality of clock signals as the selected clock signal according to the selection signal.
Claim 10
Dependent Claim
191 words
A clock timing extraction circuit for generating a clock signal synchronized with a reproduced signal in an apparatus for recording/reproducing data in/form an information recording medium, comprising: a phase synchronization feedback loop including a phase comparator for comparing said reproduced signal with a selected clock signal to generate a phase error signal and a clock signal generation circuit, having an output signal whose frequency is adjusted in order to cause said phase error signal to approach zero, and for outputting a plurality of clock signals having a phase difference therebetween, said phase comparator having an output characteristic with a plurality of phase error points of synchronization stable points present in one period; a phase difference judgment circuit for receiving the reproduced signal and for detecting a phase error when a phase acquisition operation is completed in said feedback loop on the basis of any one of said plurality of clock signals to generate a selection signal according to said phase error detected by the phase difference judgment circuit; and a selection circuit for outputting one of said plurality of clock signals as the selected clock signal according to the selection signal.
Claim 11
Dependent Claim
78 words
A clock timing extraction circuit as set forth in claim 8, wherein said clock signal generation circuit generates two clock signals having phases mutually shifted by 180 degrees, and said phase comparator has synchronization stable points for generation of a zero error signal for phase errors of -180, 0 and +180 degrees and outputs the phase error signal which linearly varies in response to variation of said phase error in a zone except for said synchronization stable points.
Claim 12
Dependent Claim
187 words
A clock timing extraction circuit for generating a clock signal synchronized with a reproduced signal in an apparatus for recording/reproducing data in/from an information recording medium, comprising: a phase comparator for comparing said reproduced signal with a selected clock signal to generate a phase error signal, said comparator having an output characteristic to output a zero phase error signal at a plurality of predetermined phase error points in a phase error range of -180 degrees to +180 degrees; a clock signal generation circuit, having an output signal whose frequency is adjusted in order to cause said phase error signal to approach zero, and for outputting a plurality of clock signals having a phase difference therebetween; a phase difference judgment circuit for receiving the reproduced signal and for detecting a phase error when said phase error signal is zero and comparing the phase error detected by the phase difference judgment circuit with a predetermined value to generate a selection signal based on a comparison result; and a selection circuit for outputting one of said plurality of clock signals as the selected clock signal according to the selection signal.
Claim 13
Dependent Claim
187 words
A clock timing extraction circuit for generating a clock signal synchronized with a reproduced signal in an apparatus for recording/reproducing data in/from an information recording medium, comprising: a phase comparator for comparing said reproduced signal with a selected clock signal to generate a phase error signal, said comparator having an output characteristic to output a zero phase error signal at a plurality of predetermined phase error points in a phase error range of -180 degrees to +180 degrees; a clock signal generation circuit, having an output signal whose frequency is adjusted in order to cause said phase error signal to approach zero, and for outputting a plurality of clock signals having a phase difference therebetween; a phase difference judgment circuit for receiving the reproduced signal and for detecting a phase error when said phase error signal is zero and comparing the phase error detected by the phase difference judgment circuit with a predetermined value to generate a selection signal based on a comparison result; and a selection circuit for outputting one of said plurality of clock signals as the selected clock signal according to the selection signal.
Claim 14
Independent Claim
237 words
An apparatus for recording/reproducing data in/from an information recording medium having an automatic gain control (AGC) circuit for limiting an amplitude of a reproduced signal from said recording medium, a clock timing extraction circuit for extracting a clock signal from an output signal of said AGC circuit, and a decoder for decoding the output signal of said AGC circuit on the basis of the clock signal extracted by said clock timing extraction circuit, said clock timing extraction circuit comprising: a phase comparator for comparing said reproduced signal with a selected clock signal to generate a phase error signal; a clock signal generation circuit, having an output signal whose frequency is adjusted in order to cause said phase error signal to approach zero, and for outputting a plurality of clock signals having phases mutually shifted; a selection circuit for outputting one of said plurality of clock signals according to a selection signal; a phase difference judgment circuit for receiving the reproduced signal and for determining which one of said plurality of clock signals has a phase error with respect to said reproduced signal that is a minimum and for generating the selection signal to select said determined one of said plurality of clock signals; and a freeze circuit for blocking an output of said phase comparator until said determined one of said plurality of clock signals as the selected clock signal having a minimum phase error is selected.
Claim 15
Independent Claim
237 words
An apparatus for recording/reproducing data in/from an information recording medium having an automatic gain control (AGC) circuit for limiting an amplitude of a reproduced signal from said recording medium, a clock timing extraction circuit for extracting a clock signal from an output signal of said AGC circuit, and a decoder for decoding the output signal of said AGC circuit on the basis of the clock signal extracted by said clock timing extraction circuit, said clock timing extraction circuit comprising: a phase comparator for comparing said reproduced signal with a selected clock signal to generate a phase error signal; a clock signal generation circuit, having an output signal whose frequency is adjusted in order to cause said phase error signal to approach zero, and for outputting a plurality of clock signals having phases mutually shifted; a selection circuit for outputting one of said plurality of clock signals according to a selection signal; a phase difference judgment circuit for receiving the reproduced signal and for determining which one of said plurality of clock signals has a phase error with respect to said reproduced signal that is a minimum and for generating the selection signal to select said determined one of said plurality of clock signals; and a freeze circuit for blocking an output of said phase comparator until said determined one of said plurality of clock signals as the selected clock signal having a minimum phase error is selected.
Claim 16
Independent Claim
237 words
An apparatus for recording/reproducing data in/from an information recording medium having an automatic gain control (AGC) circuit for limiting an amplitude of a reproduced signal from said recording medium, a clock timing extraction circuit for extracting a clock signal from an output signal of said AGC circuit, and a decoder for decoding the output signal of said AGC circuit on the basis of the clock signal extracted by said clock timing extraction circuit, said clock timing extraction circuit comprising: a phase synchronization feedback loop including a phase comparator for comparing said reproduced signal with a selected clock signal to generate a phase error signal and a clock signal generation circuit, having an output signal whose frequency is adjusted in order to cause said phase error signal to approach zero, and for outputting a plurality of clock signals having a phase difference therebetween, said phase comparator having an output characteristic with a plurality of phase error points of synchronization stable points present in one period; a phase difference judgment circuit for receiving the reproduced signal and for detecting a phase error when a phase acquisition operation is completed in said feedback loop on the basis of any one of said plurality of clock signals to generate a selection signal according to said detected phase error; and a selection circuit for outputting one of said plurality of clock signals as the selected clock signal according to the selection signal.
Claim 17
Independent Claim
237 words
An apparatus for recording/reproducing data in/from an information recording medium having an automatic gain control (AGC) circuit for limiting an amplitude of a reproduced signal from said recording medium, a clock timing extraction circuit for extracting a clock signal from an output signal of said AGC circuit, and a decoder for decoding the output signal of said AGC circuit on the basis of the clock signal extracted by said clock timing extraction circuit, said clock timing extraction circuit comprising: a phase synchronization feedback loop including a phase comparator for comparing said reproduced signal with a selected clock signal to generate a phase error signal and a clock signal generation circuit, having an output signal whose frequency is adjusted in order to cause said phase error signal to approach zero, and for outputting a plurality of clock signals having a phase difference therebetween, said phase comparator having an output characteristic with a plurality of phase error points of synchronization stable points present in one period; a phase difference judgment circuit for receiving the reproduced signal and for detecting a phase error when a phase acquisition operation is completed in said feedback loop on the basis of any one of said plurality of clock signals to generate a selection signal according to said detected phase error; and a selection circuit for outputting one of said plurality of clock signals as the selected clock signal according to the selection signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-03 | 2000-03-04 | 2000-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-03 | 2004-03-04 | 2004-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-03 | 2008-03-04 | 2008-09-03 | $7700.00 | Window Closed / Lapsed |