Patent US5553019A successfully refreshed from Google Patents.
US5553019A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Write-once read-many memory using EEPROM cells
Assignee: NXP USA Inc
•
Filing: 1995-01-23
•
Granted: 1996-09-03
•
Expires: 2015-01-23
Abstract
Abstract A write-once read-many memory system (10) for electronically securing a select portion of memory from being overwritten or erased. Memory system (10) includes one or more storage cells (25) for providing electronic storage of information. A control cell (13) is used for controlling writing and/or erasing access to the storage cells (25). Control logic (11) is provided to control access to the control cell (13). Control cell (13) and control logic (11) are used as a gate to provide selective access to storage cells (25) through write control line (19) and erase control line (21). Storage cells (25) can only be accessed when the control cell (13) in an appropriate logic state.
Inventors
- 👤 Jerry L. Sandvos
- 👤 Kenneth D. Alton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-10 01:05
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/22; G11C7/00; G11C7/24
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
200 words
A write-once read-many memory system comprising: a first memory cell for providing electronic storage of information; a second memory cell for controlling writing access to said first memory cell; access means for providing access to said second memory cell; a first bus connected to said first memory cell and said second memory cell for proving read logic information; a second bus connected to said first memory cell and said second memory cell for providing write logic information; a third bus connected to said first memory cell and said second memory cell for providing erase information; wherein said access means comprises: a first logic gate for controlling access to said second bus; a second logic gate for controlling access to said third bus; and a third logic gate for controlling access to said first logic gate and said second logic gate; and wherein said second memory cell provides selective access to said first memory cell to allow said first memory cell to write or erase said information when said second memory cell is in an appropriate logic state and further wherein said third logic gate includes an input for receiving logic information from said second memory cell and a test node.
Claim 2
Dependent Claim
200 words
A write-once read-many memory system comprising: a first memory cell for providing electronic storage of information; a second memory cell for controlling writing access to said first memory cell; access means for providing access to said second memory cell; a first bus connected to said first memory cell and said second memory cell for proving read logic information; a second bus connected to said first memory cell and said second memory cell for providing write logic information; a third bus connected to said first memory cell and said second memory cell for providing erase information; wherein said access means comprises: a first logic gate for controlling access to said second bus; a second logic gate for controlling access to said third bus; and a third logic gate for controlling access to said first logic gate and said second logic gate; and wherein said second memory cell provides selective access to said first memory cell to allow said first memory cell to write or erase said information when said second memory cell is in an appropriate logic state and further wherein said third logic gate includes an input for receiving logic information from said second memory cell and a test node.
Claim 3
Dependent Claim
37 words
A write-once read-many memory system as in claim 1 wherein said test node is positioned within a chip carrier with said first memory cell and said second memory cell for providing limited access to said test node.
Claim 4
Dependent Claim
22 words
A write-once read-many memory system as in claim 1 wherein said first memory cell is an electrically erasable programmable read only memory.
Claim 5
Dependent Claim
22 words
A write-once read-many memory system as in claim 1 wherein said second memory cell is an electronically erasable programmable read only memory.
Claim 6
Dependent Claim
19 words
A write-once read-many memory system as in claim 1 wherein said access means includes at least one logic gate.
Claim 7
Dependent Claim
22 words
A write-once read-many memory system as in claim 1 wherein said first logic gate and said second logic gate are AND gates.
Claim 8
Dependent Claim
18 words
A write-once read-many memory system as in claim 6 wherein said third logic gate is a NAND gate.
Claim 9
Dependent Claim
238 words
A memory network which includes a device which enables information to be written into a memory cell one time and read from said memory cell any number of times, said memory network comprising: at least one electronically erasable memory storage cell for storing logic information; an electronically erasable memory control cell for controlling access to said at least one electronically erasable memory storage cell; a read control bus for providing read data from said at least one electronically erasable storage cell and said electronically erasable memory control cell; a write control bus for providing write data to said at least one electronically erasable memory storage cell and said electronically erasable memory control cell; an erase control bus for providing erasing data to said at least one electronically erasable memory storage cell and said electronically erasable memory control cell; a first gate for controlling operation of said write control bus; a second gate for controlling operation of said erase control bus; a third gate for controlling access to said electronically erasable memory storage cell and said electronically erasable memory control cell; a control node connected to said third gate for providing logic information to access said third gate; and wherein said at least one electronically erasable memory storage cell and said electronically erasable memory control cell are EEPROM and further wherein said first gate and said second gate are AND gates and said third gate is a NAND gate.
Claim 10
Dependent Claim
238 words
A memory network which includes a device which enables information to be written into a memory cell one time and read from said memory cell any number of times, said memory network comprising: at least one electronically erasable memory storage cell for storing logic information; an electronically erasable memory control cell for controlling access to said at least one electronically erasable memory storage cell; a read control bus for providing read data from said at least one electronically erasable storage cell and said electronically erasable memory control cell; a write control bus for providing write data to said at least one electronically erasable memory storage cell and said electronically erasable memory control cell; an erase control bus for providing erasing data to said at least one electronically erasable memory storage cell and said electronically erasable memory control cell; a first gate for controlling operation of said write control bus; a second gate for controlling operation of said erase control bus; a third gate for controlling access to said electronically erasable memory storage cell and said electronically erasable memory control cell; a control node connected to said third gate for providing logic information to access said third gate; and wherein said at least one electronically erasable memory storage cell and said electronically erasable memory control cell are EEPROM and further wherein said first gate and said second gate are AND gates and said third gate is a NAND gate.
Claim 11
Dependent Claim
58 words
A memory network as in claim 8 wherein said control node is provided with said at least one electronically erasable memory storage cell and said electronically erasable memory control cell on an integrated circuit and said control node is inaccessible outside said integrated circuit for preventing unauthorized access to said at least one electronically erasable memory storage cell.
References Cited (Backward Citations)
US4130889A
Cited
US4152627A
Cited
US4733386A
Cited
US5175840A
Cited
US5293610A
Cited
US5229972A
Cited
US5226006A
Cited
US5381369A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-03 | 2000-03-04 | 2000-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-03 | 2004-03-04 | 2004-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-03 | 2008-03-04 | 2008-09-03 | $7700.00 | Window Closed / Lapsed |