Vertical transistor with high density DRAM cell and method of making

Claim 1

An army of vertical DRAM cells wherein each cell includes a field effect transistor having a gate electrode and source/drain elements and a capacitor comprising: a pattern of field oxide isolation in a silicon substrate wherein there are a pattern of openings to the silicon substrate; a pattern of lines of holes located within said openings to said silicon substrate, said holes of said line of holes each having a bottom and sidewalls, a pattern of parallel bit lines, wherein a bit line surrounds a line of holes, and wherein said lines of holes and bit lines are perpendicular to one another and which said bit lines and lines of holes cross at the planned locations of said vertical DRAM cells said bit lines are drain elements of said field effect transistor surrounding said holes in the surface of said substrate; source elements located at the bottom of said holes; a gate dielectric on the sidewalls and bottom surfaces of said holes; doped polysilicon stripes on the sidewalls and bottoms of said lines of holes over said gate dielectric and over said field oxide isolation thereby forming word lines; said doped polysilicon stripes providing gate electrodes on the sidewalls on said holes, a silicon nitride layer over said doped polysilicon stripes; contact openings in the bottoms of each of said holes through said silicon nitride layer and doped polysilicon stripes, said doped polysilicon stripes establishing gate electrodes in said holes and word line patterns over the said field oxide isolation; first silicon oxide spacers over the sidewalls of each of said contact openings in said silicon nitride layer and said doped polysilicon stripes; a capacitor node polysilicon electrode in each of said holes and in contact to said source element through said contact opening; a capacitor dielectric over each of said capacitor node polysilicon electrodes; and a capacitor polysilicon plate electrode over each of said capacitor dielectrics to complete said vertical DRAM cell.