US5551076A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit and method of series biasing a single-ended mixer
Assignee: NXP USA Inc
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Filing: 1994-09-06
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Granted: 1996-08-27
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Expires: 2014-09-06
Abstract
Abstract A mixer circuit (10) combines a buffered RF signal with the LO signal at the gate of a mixing transistor (20) for providing sum and difference product terms as the IF output signal. An inductor (46) provides a DC signal path between the source of the mixing transistor and the drain of the buffering transistor (14) to share the same operating current and thereby reduce power consumption in the mixer. The DC path inductor provides a high impedance to block the RF signal and LO signal. A bias circuit (26, 28) sets the bias point at the gate of the mixing transistor to a mid-point value between V DD and ground potential. In disable mode, the bias point of the mixing transistor is sufficiently low that the LO signal does not have sufficient power to turn on buffering and mixing transistors that could generate mixing products at the IF output.
Inventors
- 👤 Fred H. Bonn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 13:59
CPC Classifications
H; H03; H03D; H03D7/00; H03D7/12; H03D7/125
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
132 words
A mixer circuit, comprising: a first transistor having a gate, a drain and a source, said source being coupled for receiving an RF signal, said gate being coupled to a first power supply conductor; a second transistor having a gate, a drain and a source, said gate being coupled to said drain of said first transistors said gate being further coupled for receiving an LO signal, said source being coupled to said first power supply conductor, said drain providing an IF output signal; and circuit means coupled between said source of said second transistor and said drain of said first transistor for providing a DC signal path between said source of said second transistor and said drain of said first transistor to allow said first and second transistors to share operating current.
Claim 2
Dependent Claim
132 words
A mixer circuit, comprising: a first transistor having a gate, a drain and a source, said source being coupled for receiving an RF signal, said gate being coupled to a first power supply conductor; a second transistor having a gate, a drain and a source, said gate being coupled to said drain of said first transistors said gate being further coupled for receiving an LO signal, said source being coupled to said first power supply conductor, said drain providing an IF output signal; and circuit means coupled between said source of said second transistor and said drain of said first transistor for providing a DC signal path between said source of said second transistor and said drain of said first transistor to allow said first and second transistors to share operating current.
Claim 3
Dependent Claim
29 words
The mixer circuit of claim 1 wherein said circuit means includes a first inductor coupled between said source of said second transistor and said drain of said first transistor.
Claim 4
Dependent Claim
25 words
The mixer circuit of claim 2 further including a first capacitor coupled between said source of said second transistor and said first power supply conductor.
Claim 5
Dependent Claim
41 words
The mixer circuit of claim 3 further including: a first resistor coupled between an enable input and said gate of said second transistor; and a second resistor coupled between said gate of said second transistor and said first power supply conductor.
Claim 6
Dependent Claim
26 words
The mixer circuit of claim 4 further including a second capacitor coupled between said drain of said second transistor and said source of said second transistor.
Claim 7
Dependent Claim
26 words
The mixer circuit of claim 5 further including a third resistor coupled between said source of said first transistor and said gate of said first transistor.
Claim 8
Dependent Claim
49 words
The mixer circuit of claim 6 further including: a third capacitor; a second inductor serially coupled with said third capacitor between said LO signal and said gate of said second transistor; and a fourth capacitor coupled between said gate of said second transistor and said first power supply conductor.
Claim 9
Dependent Claim
42 words
The mixer circuit of claim 7 further including: a third inductor coupled between a second power supply conductor and said drain of said second transistor; and a fifth capacitor coupled between said first power supply conductor and said second power supply conductor.
Claim 10
Dependent Claim
26 words
The mixer circuit of claim 8 further including a sixth capacitor coupled between said drain of said first transistor and said gate of said second transistor.
Claim 11
Independent Claim
81 words
A method of mixing an RF signal with an LO signal, comprising the steps of: buffering the RF signal through a first transistor for providing a buffered RF signal; mixing said buffered RF signal with the LO signal in a second transistor for providing an IF output signal; and providing a DC signal path between a conduction path of said first transistor and a conduction path of said second transistor to allow said first and second transistors to share operating current.
Claim 12
Independent Claim
81 words
A method of mixing an RF signal with an LO signal, comprising the steps of: buffering the RF signal through a first transistor for providing a buffered RF signal; mixing said buffered RF signal with the LO signal in a second transistor for providing an IF output signal; and providing a DC signal path between a conduction path of said first transistor and a conduction path of said second transistor to allow said first and second transistors to share operating current.
Claim 13
Dependent Claim
24 words
The method of claim 10 further comprising the step of blocking said buffered RF signal and the LO signal through said DC signal path.
Claim 14
Dependent Claim
133 words
A mixer circuit, comprising: a first transistor having a gate, a drain and a source, said source being coupled for receiving an RF signal, said gate being coupled to a first power supply conductor; a second transistor having a gate, a drain and a source, said gate being coupled to said drain of said first transistor, said gate being further coupled for receiving an LO signal, said source being coupled to said first power supply conductor, said drain providing an IF output signal; and a first inductor coupled between said source of said second transistor and said drain of said first transistor for providing a DC signal path between said source of said second transistor and said drain of said first transistor to allow said first and second transistors to share operating current.
Claim 15
Dependent Claim
133 words
A mixer circuit, comprising: a first transistor having a gate, a drain and a source, said source being coupled for receiving an RF signal, said gate being coupled to a first power supply conductor; a second transistor having a gate, a drain and a source, said gate being coupled to said drain of said first transistor, said gate being further coupled for receiving an LO signal, said source being coupled to said first power supply conductor, said drain providing an IF output signal; and a first inductor coupled between said source of said second transistor and said drain of said first transistor for providing a DC signal path between said source of said second transistor and said drain of said first transistor to allow said first and second transistors to share operating current.
Claim 16
Dependent Claim
25 words
The mixer circuit of claim 12 further including a first capacitor coupled between said source of said second transistor and said first power supply conductor.
Claim 17
Dependent Claim
42 words
The mixer circuit of claim 13 further including: a first resistor coupled between an enable input and said gate of said second transistor; and a second resistor coupled between said gate of said second transistor and said source of said second transistor.
Claim 18
Dependent Claim
26 words
The mixer circuit of claim 14 further including a second capacitor coupled between said drain of said second transistor and said source of said second transistor.
Claim 19
Dependent Claim
25 words
The mixer circuit of claim 15 further including a third resistor coupled between said source of said first transistor and said first power supply conductor.
Claim 20
Dependent Claim
74 words
The mixer circuit of claim 16 further including: a third transistor having a gate, a drain and a source, said gate being coupled to said first power supply conductor, said drain being coupled to said drain of said first transistor; a third capacitor coupled between said LO signal and said source of said third transistor; and a fourth resistor coupled between said source of said third transistor and said gate of said third transistor.
Claim 21
Dependent Claim
42 words
The mixer circuit of claim 17 further including: a second inductor coupled between a second power supply conductor and said drain of said second transistor; and a fourth capacitor coupled between said first power supply conductor and said second power supply conductor.
Claim 22
Dependent Claim
26 words
The mixer circuit of claim 18 further including a fifth capacitor coupled between said drain of said first transistor and said gate of said second transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-27 | 2000-02-26 | 2000-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-27 | 2004-02-26 | 2004-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-27 | 2008-02-26 | 2008-08-27 | $7700.00 | Window Closed / Lapsed |