Semiconductor memory device with synchronous dram whose speed grade is not limited

Claim 1

A semiconductor memory device which includes a burst counter for latching an external address signal and generating an internal address signal in synchronism to a first clock signal having a predetermined cycle period; a column decoder for decoding the internal address signal; a column switch latch portion which assumes a data-through state with the supply of the first clock signal being cut-off when a mode signal internally supplied is active, and latches the output of the column decoder in synchronism to the first clock signal when the mode signal is inactive; and an output data latch circuit for reading out memory data designated by the output of the column switch latch portion under control of a read command and latching the read-out data in synchronism to the first clock signal, and in which, when the mode signal is inactive, a first operation mode is set to read out the data designated by the internal address signal in synchronism to the first clock signal that is N (N being an integer not less than 2) clock cycles after a latch timing of the burst counter, and the read-out data is outputted from the output data latch circuit, and when a second clock signal having a longer cycle period than the first clock signal is supplied in lieu of the first clock signal and also when the mode signal is inactive, a second operation mode is set to read out the data designated by the internal address signal in synchronism to the second clock signal N-1 clock cycles after the latch timing of the burst counter, and the readout data is outputted from the output data latch circuit, said semiconductor memory device comprising: a delay circuit for delaying said second clock signal by a predetermined period of time under said second operation mode; and an output control means for controlling the data to be outputted from said output data latch circuit in synchronism to said second clock signal that is delayed by said delay circuit.