US5550496A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed I/O circuit having a small voltage swing and low power dissipation for high I/O count applications
Assignee: Hewlett Packard Development Co LP
•
Filing: 1995-07-31
•
Granted: 1996-08-27
•
Expires: 2015-07-31
Abstract
Abstract An interchip high speed I/O circuit having a low voltage swing and on-chip transmission line terminations. The present invention provides a high speed I/O circuit that uses a small voltage swing to keep power dissipation in the overall system to a minimum and particularly in the transmission line termination loads. A differential receiver circuit compares a data signal input to a reference signal, both sent from a driver chip, to determine the appropriate output response. Both the data signal and the reference signal are current controlled which reduces the di/dt noise generated by parasitic inductances.
Inventors
- 👤 Alan R. Desroches
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:18
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/0264; H04L25/028; H03; H03F; H03F3/00; H03F3/72; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K19/018528; H03K5/00; H03K5/01; H03K5/02; H03K5/026; H04L25/0292; H04L25/0298; H04L25/0272
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
192 words
An interchip high speed communications apparatus comprising: a first integrated circuit having a controlled current data driver having an output and the first integrated circuit also having a reference driver having an output; a second integrated circuit having a differential receiver with a data input, a reference input and the differential receiver also having an output; a data transmission line electrically connecting the output of the data driver to the data input of the differential receiver; a reference transmission line electrically connecting the output of the reference driver to the reference input of the differential receiver; and the differential receiver comprising a comparator for comparing said data input voltage with said reference input voltage and operative to output a first voltage level in response to a voltage on the data input being higher than a voltage on the reference input and the differential receiver being operative to output a second voltage level in response to a voltage on the data input being lower than a voltage on the reference input; and a termination device fabricated as part of said second integrated circuit, wherein the power dissipation on said communications apparatus is minimized.
Claim 2
Dependent Claim
192 words
An interchip high speed communications apparatus comprising: a first integrated circuit having a controlled current data driver having an output and the first integrated circuit also having a reference driver having an output; a second integrated circuit having a differential receiver with a data input, a reference input and the differential receiver also having an output; a data transmission line electrically connecting the output of the data driver to the data input of the differential receiver; a reference transmission line electrically connecting the output of the reference driver to the reference input of the differential receiver; and the differential receiver comprising a comparator for comparing said data input voltage with said reference input voltage and operative to output a first voltage level in response to a voltage on the data input being higher than a voltage on the reference input and the differential receiver being operative to output a second voltage level in response to a voltage on the data input being lower than a voltage on the reference input; and a termination device fabricated as part of said second integrated circuit, wherein the power dissipation on said communications apparatus is minimized.
Claim 3
Dependent Claim
61 words
An apparatus as in claim 1 wherein: the controlled current data driver sends either a high voltage level or a low voltage level to the differential receiver; and the reference driver sends an approximately constant voltage to the differential receiver where the approximately constant voltage has a value less than the high voltage level and more than the low voltage level.
Claim 4
Dependent Claim
35 words
An apparatus as in claim 2 wherein: the approximately constant voltage from the reference driver tracks minor voltage variations in the value of the high or low voltage levels from the constant current data driver.
Claim 5
Dependent Claim
29 words
An apparatus as in claim 3 wherein: a common constant current source controls the amount of current either the reference driver or the controlled current data driver can sink.
Claim 6
Dependent Claim
275 words
An interchip high speed communications apparatus comprising: a first integrated circuit having a controlled current data driver having an output and the first integrated circuit also having a controlled current reference driver having an output; a second integrated circuit having a differential receiver with a data input, a reference input and the differential receiver also having an output; a data transmission line electrically connecting the output of the constant current data driver to the data input of the differential receiver; a reference transmission line electrically connecting the output of the constant current reference driver to the reference input of the differential receiver; the differential receiver being operative to output a first voltage level in response to a voltage on the data input being higher than a voltage on the reference input and the differential receiver being operative to output a second voltage level in response to a voltage on the data input being lower than a voltage on the reference input; the second integrated circuit having a first resistive termination device connected to the reference transmission line and connected to the reference input of the differential receiver where the first resistive device terminates the reference transmission line with approximately the same resistance as the characteristic impedance of the reference transmission line; the second integrated circuit having a second resistive termination device connected to the data transmission line and connected to the data input of the differential receiver where the second resistive device terminates the data transmission line with approximately the same resistance as the characteristic impedance of the data transmission line; and first and second termination devices fabricated as part of said second integrated circuit.
Claim 7
Dependent Claim
275 words
An interchip high speed communications apparatus comprising: a first integrated circuit having a controlled current data driver having an output and the first integrated circuit also having a controlled current reference driver having an output; a second integrated circuit having a differential receiver with a data input, a reference input and the differential receiver also having an output; a data transmission line electrically connecting the output of the constant current data driver to the data input of the differential receiver; a reference transmission line electrically connecting the output of the constant current reference driver to the reference input of the differential receiver; the differential receiver being operative to output a first voltage level in response to a voltage on the data input being higher than a voltage on the reference input and the differential receiver being operative to output a second voltage level in response to a voltage on the data input being lower than a voltage on the reference input; the second integrated circuit having a first resistive termination device connected to the reference transmission line and connected to the reference input of the differential receiver where the first resistive device terminates the reference transmission line with approximately the same resistance as the characteristic impedance of the reference transmission line; the second integrated circuit having a second resistive termination device connected to the data transmission line and connected to the data input of the differential receiver where the second resistive device terminates the data transmission line with approximately the same resistance as the characteristic impedance of the data transmission line; and first and second termination devices fabricated as part of said second integrated circuit.
Claim 8
Dependent Claim
21 words
An apparatus as in claim 5 wherein: the first and second resistive devices are transistors constructed on the second integrated circuit.
Claim 9
Dependent Claim
15 words
An apparatus as in claim 6 wherein: the transistors are metal oxide silicon (MOS) transistors.
Claim 10
Dependent Claim
63 words
An apparatus as in claim 7 wherein: the controlled current data driver sends either a high voltage level or a low voltage level to the differential receiver; and the controlled current reference driver sends an approximately constant voltage to the differential receiver where the approximately constant voltage has a value less than the high voltage level and more than the low voltage level.
Claim 11
Dependent Claim
35 words
An apparatus as in claim 8 wherein: the approximately constant voltage from the reference driver tracks minor voltage variations in the value of the high or low voltage levels from the constant current data driver.
Claim 12
Dependent Claim
50 words
An apparatus as in claim 6 wherein: the first resistive device sources a first current having a maximum value to the controlled current data driver and the second resistive device sources a current to the controlled reference driver having a value less than the maximum value of the first current.
Claim 13
Dependent Claim
27 words
An apparatus as in claim 10 wherein: the second resistive sources a current having a value of approximately one-half of the maximum value of the first current.
References Cited (Backward Citations)
US4697095A
Cited
US4780629A
Cited
US4756006A
Cited
US4945267A
Cited
US5378950A
Cited
US5461333A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-27 | 2000-02-26 | 2000-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-27 | 2004-02-26 | 2004-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-27 | 2008-02-26 | 2008-08-27 | $7700.00 | Window Closed / Lapsed |