US5461333A
Expired / Lapsed
US
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Multi-chip modules having chip-to-chip interconnections with reduced signal voltage level and swing
Assignee: Agere Systems LLC
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Filing: 1994-02-24
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Granted: 1995-10-24
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Expires: 2014-02-24
Abstract
Abstract A multi-chip module is composed of two or more integrated-circuit chips located on a substrate such as a dielectrically coated silicon substrate. The chips are interconnected by means of transmission wiring lines. At least some of the chips contain one or more input buffer circuits, each composed of two branches ("legs"). Each such branch contains, in one embodiment, an n-channel MOS transistor connected in series with a pair of series-connected p-channel MOS transistors--whereby, in each such branch, one of the p-channel MOS transistors is located between (intermediate) the other of the p-channel MOS transistors and the n-channel MOS transistor of that same branch. On the other hand, in each buffer circuit, the intermediate p-channel MOS transistors of both branches are cross-coupled. Each of the n-channel MOS transistors is connected in a common gate configuration to receive one of the complementary input signals coming from the transmission wiring lines, and the other of the p-channel transistors in each branch is connected in a common source configuration to receive the other of the complementary input signals.
Inventors
- 👤 Joseph H. Condon
- 👤 Robert C. Frye
- 👤 Thaddeus J. Gabara
- 👤 King L. Tai
- 👤 Scott C. Knauer, deceased
- 👤 executor Carroll H. Knauer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:32
CPC Classifications
H; H10; H10W; H10W90/00; H03; H03K; H03K3/00; H03K3/01; H03K3/012; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/356052; H03K3/356104; H03K3/356113; H03K3/356147; H10W90/701; H10W90/721; H10W90/724
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
232 words
Input buffer circuitry, responsive to complementary first and second incoming signals, including (a) first and second parallel branches, each of the branches having a first transistor of a first channel type connected in series with second and third transistors, both of a second channel type that is opposite from the first channel type, and each of the first, second, and third transistors having a gate terminal, a source terminal, and a drain terminal, the first transistors of the first and second branches being located at an extremity of said branches, respectively; (b) first electrically conductive means, connecting the gate terminal of the third transistor in the first branch to the source terminal of the first transistor in the second branch, and connected to receive the first incoming signal; (c) second electrically conductive means, electrically connecting the gate terminal of the third transistor in the second branch to the source terminal of the first transistor in the first branch, and connected to receive the second incoming signal; and (d) third and fourth electrically conductive means, connecting the gate terminals of the second transistors in the first and second branches to the drain terminals of the first transistors in the second and first branches, respectively, a node for providing an output terminal located on the input buffer circuitry e) fifth electrically conductive means connecting the gates of said first transistors to a voltage potential.
Claim 2
Dependent Claim
232 words
Input buffer circuitry, responsive to complementary first and second incoming signals, including (a) first and second parallel branches, each of the branches having a first transistor of a first channel type connected in series with second and third transistors, both of a second channel type that is opposite from the first channel type, and each of the first, second, and third transistors having a gate terminal, a source terminal, and a drain terminal, the first transistors of the first and second branches being located at an extremity of said branches, respectively; (b) first electrically conductive means, connecting the gate terminal of the third transistor in the first branch to the source terminal of the first transistor in the second branch, and connected to receive the first incoming signal; (c) second electrically conductive means, electrically connecting the gate terminal of the third transistor in the second branch to the source terminal of the first transistor in the first branch, and connected to receive the second incoming signal; and (d) third and fourth electrically conductive means, connecting the gate terminals of the second transistors in the first and second branches to the drain terminals of the first transistors in the second and first branches, respectively, a node for providing an output terminal located on the input buffer circuitry e) fifth electrically conductive means connecting the gates of said first transistors to a voltage potential.
Claim 3
Dependent Claim
36 words
The input buffer circuitry of claim 1 in which all the transistors of the first channel type are p-channel MOS transistors and in which all the transistors of the second channel type are n-channel MOS transistors.
Claim 4
Dependent Claim
109 words
The input buffer circuitry of claim 2 further including first and second voltage sources, the first voltage source being connected to the source terminal of each of the third transistors in the first and second branches, the second voltage source being connected to the gate terminal of each of the first transistors in both the first and the second branches, whereby in response to the complementary first and second input signals, an output signal is generated at the output terminal of the input buffer circuitry such that each of the complementary first and second incoming signals has a signal level that is less than that of the output signal.
Claim 5
Dependent Claim
58 words
A module comprising first and second integrated circuit chips, the second chip including input buffer circuitry in accordance with claim 3, and the module further including first and second transmission lines that electrically connect complementary first and second output terminals of the first chip separately with the first and second electrically conductive means, respectively, of the second chip.
Claim 6
Dependent Claim
45 words
The module of claim 4 in which the first chip comprises: an output buffer circuitry for developing the complementary first and second incoming signals, and for delivering the complementary first and second incoming signals to the first and second output terminals of the first chip.
Claim 7
Dependent Claim
58 words
A module comprising first and second integrated circuit chips, the second chip including input buffer circuitry in accordance with claim 2, and the module further including first and second transmission lines that electrically connect complementary first and second output terminals of the first chip separately with the first and second electrically conductive means, respectively, in the second chip.
Claim 8
Dependent Claim
45 words
The module of claim 6 in which the first chip comprises: an output buffer circuitry for developing the complementary first and second input signals, and for delivering the complementary first and second input signals to the first and second output terminals of the first chip.
Claim 9
Dependent Claim
36 words
The input buffer circuitry of claim 1 in which all the transistors of the first channel type are n-channel MOS transistors and in which all the transistors of the second channel type are p-channel MOS transistors.
Claim 10
Dependent Claim
109 words
The input buffer circuitry of claim 8 further including first and second voltage sources, the first voltage source being connected to the source terminal of each of the third transistors in both the first and the second branches, the second voltage source being connected to the gate terminal of each of the first transistors, in the first and second branches, whereby in response to the complementary first and second input signals, an output signal is generated at the output terminal of the input buffer circuitry such that each of the complementary first and second incoming signals has a signal level that is less than that of the output signal.
Claim 11
Dependent Claim
58 words
A module comprising first and second integrated circuit chips, the second chip including input buffer circuitry in accordance with claim 9, and the module further including first and second transmission lines that electrically connect complementary first and second output terminals of the first chip separately with the first and second electrically conductive means, respectively, of the second chip.
Claim 12
Dependent Claim
46 words
The module of claim 10 in which the first chip comprises: an output buffer circuitry adapted for developing the complementary first and second incoming signals, and for delivering the complementary first and second incoming signals to the first and second output terminals of the first chip.
Claim 13
Dependent Claim
58 words
A module comprising first and second integrated circuit chips, the second chip including input buffer circuitry in accordance with claim 8, and the module further including first and second transmission lines that electrically connect complementary first and second output terminals of the first chip separately with the first and second electrically conductive means, respectively, in the second chip.
Claim 14
Dependent Claim
45 words
The module of claim 12 in which the first chip comprises: an output buffer circuitry for developing the complementary first and second input signals, and for delivering the complementary first and second input signals to the first and second output terminals of the first chip.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-23 | 1999-04-24 | 1999-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-23 | 2003-04-24 | 2003-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-23 | 2007-04-24 | 2007-10-24 | $7700.00 | Window Closed / Lapsed |