US5548746A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Non-contiguous mapping of I/O addresses to use page protection of a process
Assignee: International Business Machines Corp
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Filing: 1993-11-12
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Granted: 1996-08-20
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Expires: 2013-11-12
Abstract
Abstract A system and method for protecting individual segments of a contiguous I/O address space on a system bus using the page access protection resources of a processor operating on a processor bus address space. The contiguous I/O address space is segmented and mapped by translation into the processor address space by distributing I/O segments non-contiguously among successive processor bus pages. Individual I/O address space segments, as may be associated with I/O ports, are protected directly by the processor through the selective enablement of page protection for correspondingly mapped ports.
Inventors
- 👤 Gary D. Carpenter
- 👤 Mark E. Dean
- 👤 Marc R. Faucher
- 👤 James C. Peterson
- 👤 Howard C. Tanner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:30
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/14; G06F12/1416; G06F12/1425; G06F12/1441; G06F12/02; G06F12/0223; G06F12/0292; G06F12/08; G06F12/10; G06F12/1081; G06F2212/00; G06F2212/20; G06F2212/206
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
114 words
In a computer having a processor with processor address space and a system bus with system bus address space, a system bus address space protection system, comprising: means within the processor for selectively inhibiting access to individual pages or blocks of the processor address space; means for translating non-contiguous segments in individual pages or blocks of the processor address space into a band of contiguous segments of the system bus address space; and means for preventing access to individually selected segments from the band of contiguous segments of the system bus address space by inhibiting access within the processor to pages or blocks of the processor address space relating to the individually selected segments.
Claim 2
Dependent Claim
114 words
In a computer having a processor with processor address space and a system bus with system bus address space, a system bus address space protection system, comprising: means within the processor for selectively inhibiting access to individual pages or blocks of the processor address space; means for translating non-contiguous segments in individual pages or blocks of the processor address space into a band of contiguous segments of the system bus address space; and means for preventing access to individually selected segments from the band of contiguous segments of the system bus address space by inhibiting access within the processor to pages or blocks of the processor address space relating to the individually selected segments.
Claim 3
Dependent Claim
22 words
The apparatus recited in claim 1, wherein the band of contiguous segments of the system bus address space is I/O address space.
Claim 4
Dependent Claim
22 words
The apparatus recited in claim 2, wherein the I/O address space translates into multiple substantially equal segments of the processor address space.
Claim 5
Dependent Claim
23 words
The apparatus recited in claim 1, wherein the non-contiguous segments in individual pages or blocks of the processor address space correspond in size.
Claim 6
Dependent Claim
20 words
The apparatus recited in claim 4, wherein the processor address space and the system bus address space correspond in size.
Claim 7
Dependent Claim
67 words
A computer I/O address space protection system, comprising: a processor with block or page access protection connected to a processor bus with processor address space comprised of multiple blocks or pages; system bus with a contiguous I/O address space comprised of multiple segments; and means for translating non-contiguous segments in individual blocks or pages of the processor address space into contiguous segments of the I/O address space.
Claim 8
Dependent Claim
67 words
A computer I/O address space protection system, comprising: a processor with block or page access protection connected to a processor bus with processor address space comprised of multiple blocks or pages; system bus with a contiguous I/O address space comprised of multiple segments; and means for translating non-contiguous segments in individual blocks or pages of the processor address space into contiguous segments of the I/O address space.
Claim 9
Dependent Claim
25 words
The system recited in claim 6, wherein the non-contiguous segments in individual blocks or pages of the processor address space are substantially equal in size.
Claim 10
Dependent Claim
19 words
The system recited in claim 7, wherein the processor bus and the system bus address space correspond in size.
Claim 11
Dependent Claim
114 words
In a computer having a processor with processor address space and a system bus with system bus address space, a method of protecting segments of contiguous system bus address space in the computer, comprising the steps of: operating the processor to provide a page or block protection mode; translating non-contiguous segments in individual pages or blocks of the processor address space into a band of contiguous segments of the system bus address space and; selectively preventing access to individual segments from the band of contiguous segments of the system bus address space by selectively enabling the page or block protection mode for pages or blocks of processor address space relating to the individual segments.
Claim 12
Dependent Claim
114 words
In a computer having a processor with processor address space and a system bus with system bus address space, a method of protecting segments of contiguous system bus address space in the computer, comprising the steps of: operating the processor to provide a page or block protection mode; translating non-contiguous segments in individual pages or blocks of the processor address space into a band of contiguous segments of the system bus address space and; selectively preventing access to individual segments from the band of contiguous segments of the system bus address space by selectively enabling the page or block protection mode for pages or blocks of processor address space relating to the individual segments.
Claim 13
Dependent Claim
22 words
The method recited in claim 9, wherein the band of contiguous segments of the system bus address space is I/O address space.
Claim 14
Dependent Claim
23 words
The method recited in claim 10, wherein the non-contiguous segments in individual pages or blocks of the processor address space correspond in size.
Claim 15
Dependent Claim
19 words
The method recited in claim 11, wherein the processor address space and system bus address space correspond in size.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-20 | 2000-02-19 | 2000-08-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-20 | 2004-02-19 | 2004-08-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-20 | 2008-02-19 | 2008-08-20 | $7700.00 | Window Closed / Lapsed |