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US4042913A
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Address key register load/store instruction system
Assignee: International Business Machines Corp
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Filing: 1976-04-30
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Granted: 1977-08-16
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Expires: 1996-04-30
Abstract
Abstract The disclosure describes instruction operated controls for loading or storing address key values into or from one or more address key register sections in a key-register-controlled addressing system. The controls load or store one or all key register sections of an address key register (AKR) in a processor from or to a word in either a main memory or a general purpose register (GPR). Both the load or store controls are operated by the same instruction format, in which one field indicates whether the operation is to be a load or store of the designated AKR section(s). Another field designates one AKR section, or all AKR sections, which are to be loaded or stored. A still further field designates whether the operation is to be from or to main memory or a GPR. The disclosure provides circuits which operate with microcode to perform these operations.
Inventors
- 👤 Richard Eugene Birney
- 👤 Michael Ian Davis
- 👤 Lynn Allan Graybiel
- 👤 Robert Allen Hood
- 👤 Samuel Kahn
- 👤 William Steese Osborne
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 03:19
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3004; G06F9/30043; G06F12/00; G06F12/14; G06F12/1458; G06F13/00; G06F13/10; G06F13/12; G06F13/122
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
298 words
Addressability definition control for a data processor for executing an address key register (AKR) load instruction for loading address keys into an address key register (AKR) from a general register or a main memory location, the address keys contained in the address key register determining the addressability currently available to the processor, the addressability definition control including a plurality of bistable storage positions for each of plural key sections in the AKR for registering an address key in each section, the registered keys in the AKR defining the current addressability of the processor, a plurality of single key ingates separately connected to inputs of each of the key sections in the AKR, a multiple key ingate connected to inputs of all of the single key sections, a plurality of single key signal lines respectively connected to the plurality of single key ingates, and all of the single key signal lines also connected to the multiple key ingate, a control store decoder having as outputs single and multiple key ingate control lines for connecting control signals activated by microcode received from a control store to the respective ingates, the decoder activating one of the control lines selected by the instruction, means for outputting address signals from the instruction for selecting a general register or a main memory location containing required address key signals, means for connecting the selected general register or memory location to a processor data path, and any ingate control line activated by the decoder in response to the instruction to select any single key section or all key sections for transferring one or multiple address key signals into the AKR from the processor data path, which is currently connected to a selected general register or memory location to load the processor with one or plural addressabilities.
Claim 2
Dependent Claim
298 words
Addressability definition control for a data processor for executing an address key register (AKR) load instruction for loading address keys into an address key register (AKR) from a general register or a main memory location, the address keys contained in the address key register determining the addressability currently available to the processor, the addressability definition control including a plurality of bistable storage positions for each of plural key sections in the AKR for registering an address key in each section, the registered keys in the AKR defining the current addressability of the processor, a plurality of single key ingates separately connected to inputs of each of the key sections in the AKR, a multiple key ingate connected to inputs of all of the single key sections, a plurality of single key signal lines respectively connected to the plurality of single key ingates, and all of the single key signal lines also connected to the multiple key ingate, a control store decoder having as outputs single and multiple key ingate control lines for connecting control signals activated by microcode received from a control store to the respective ingates, the decoder activating one of the control lines selected by the instruction, means for outputting address signals from the instruction for selecting a general register or a main memory location containing required address key signals, means for connecting the selected general register or memory location to a processor data path, and any ingate control line activated by the decoder in response to the instruction to select any single key section or all key sections for transferring one or multiple address key signals into the AKR from the processor data path, which is currently connected to a selected general register or memory location to load the processor with one or plural addressabilities.
Claim 3
Dependent Claim
303 words
Addressability status control for a data processor for executing an address key register (AKR) store instruction for storing address keys from an address key register (AKR) into a general register or a main memory location, the address keys contained in the address key register determining the addressability currently available to the processor, the addressability status control including, a plurality of bistable storage positions for each of plural key sections in the AKR for registering an address key in each section, the registered keys in the AKR defining the current addressability of the processor, a plurality of single key outgates separately connected to outputs of each of the key sections in the AKR, a multiple key outgate connected to outputs of all of the single key sections, a plurality of single key signal lines respectively connected to the plurality of single key outgates, and all of the single key signal lines also connected to the multiple key outgate, a control store decoder having as outputs single and multiple key outgate control lines for connecting control signals activated by microcode received from a control store to the respective outgates, the decoder activating one of the control lines selected by the instruction, means for outputting address signals from the instruction for selecting a general register or a main memory location which is to receive required address key signals, means for connecting the selected general register or memory location to a processor data path, and any outgate control line activated by the decoder in response to the instruction to select any single key section or all key sections for transferring one or multiple address key signals from the AKR to the processor data path, which is currently connected to a selected general register or memory location in which the current addressability status of the processor is stored.
Claim 4
Dependent Claim
303 words
Addressability status control for a data processor for executing an address key register (AKR) store instruction for storing address keys from an address key register (AKR) into a general register or a main memory location, the address keys contained in the address key register determining the addressability currently available to the processor, the addressability status control including, a plurality of bistable storage positions for each of plural key sections in the AKR for registering an address key in each section, the registered keys in the AKR defining the current addressability of the processor, a plurality of single key outgates separately connected to outputs of each of the key sections in the AKR, a multiple key outgate connected to outputs of all of the single key sections, a plurality of single key signal lines respectively connected to the plurality of single key outgates, and all of the single key signal lines also connected to the multiple key outgate, a control store decoder having as outputs single and multiple key outgate control lines for connecting control signals activated by microcode received from a control store to the respective outgates, the decoder activating one of the control lines selected by the instruction, means for outputting address signals from the instruction for selecting a general register or a main memory location which is to receive required address key signals, means for connecting the selected general register or memory location to a processor data path, and any outgate control line activated by the decoder in response to the instruction to select any single key section or all key sections for transferring one or multiple address key signals from the AKR to the processor data path, which is currently connected to a selected general register or memory location in which the current addressability status of the processor is stored.
Claim 5
Dependent Claim
400 words
Addressability definition and status control for a data processor for executing an address key register (AKR), load or store instruction for loading or storing address keys into or from an address key register (AKR) respectively from or into a general register or a main memory location, the address keys contained in the address key register determining the addressability currently available to the processor, the addressability definition and status control including, a plurality of bistable storage positions for each of plural key sections in the AKR for registering an address key in each section, the registered keys in the AKR defining the current addressability of the processor, a plurality of single key ingates separately connected to inputs of each of the key sections in the AKR, a multiple key ingate connected to inputs of all of the single key sections, a plurality of single key signal lines respectively connected to the plurality of single key ingates, and all of the single key signal lines also connected to the multiple key ingate, a plurality of single key outgates separately connected to outputs of each of the key sections in the AKR, a multiple key outgate connected to outputs of all of the single key sections, the plurality of single key signal lines also respectively connected to the plurality of single key outgates, and all of the single key signal lines also connected to the multiple key outgate, a control store decoder operating under instruction control and having as outputs single and multiple key ingate and outgate control lines for connecting control signals activated by microcode received from a control store to the respective ingates and outgates, the instruction controlling which outgate or ingate control line is activated by the decoder, means for outputting address signals from the instruction for selecting a general register or a main memory location containing required address key signals, means for connecting the selected general register or memory location to a processor data path, and the ingate or outgate control line activated by the decoder in response to the instruction to select one of the ingates or outgates for transferring one or multiple address key signals into or from the AKR respectively from or into the processor data path, which is currently connected to the selected general register or memory location to respectively load the addressability of the processor or store the current addressability status of the processor.
Claim 6
Dependent Claim
400 words
Addressability definition and status control for a data processor for executing an address key register (AKR), load or store instruction for loading or storing address keys into or from an address key register (AKR) respectively from or into a general register or a main memory location, the address keys contained in the address key register determining the addressability currently available to the processor, the addressability definition and status control including, a plurality of bistable storage positions for each of plural key sections in the AKR for registering an address key in each section, the registered keys in the AKR defining the current addressability of the processor, a plurality of single key ingates separately connected to inputs of each of the key sections in the AKR, a multiple key ingate connected to inputs of all of the single key sections, a plurality of single key signal lines respectively connected to the plurality of single key ingates, and all of the single key signal lines also connected to the multiple key ingate, a plurality of single key outgates separately connected to outputs of each of the key sections in the AKR, a multiple key outgate connected to outputs of all of the single key sections, the plurality of single key signal lines also respectively connected to the plurality of single key outgates, and all of the single key signal lines also connected to the multiple key outgate, a control store decoder operating under instruction control and having as outputs single and multiple key ingate and outgate control lines for connecting control signals activated by microcode received from a control store to the respective ingates and outgates, the instruction controlling which outgate or ingate control line is activated by the decoder, means for outputting address signals from the instruction for selecting a general register or a main memory location containing required address key signals, means for connecting the selected general register or memory location to a processor data path, and the ingate or outgate control line activated by the decoder in response to the instruction to select one of the ingates or outgates for transferring one or multiple address key signals into or from the AKR respectively from or into the processor data path, which is currently connected to the selected general register or memory location to respectively load the addressability of the processor or store the current addressability status of the processor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-15 | 1981-02-14 | 1981-08-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-15 | 1985-02-14 | 1985-08-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-15 | 1989-02-14 | 1989-08-16 | $7700.00 | Window Closed / Lapsed |