US3855580A
Expired / Lapsed
US
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Memory system including addressing arrangement
Assignee: 148074 HOLDINGS CANADA Ltd
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Filing: 1974-01-11
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Granted: 1974-12-17
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Expires: 1994-01-11
Abstract
Abstract Read only memory system employing four arrays of memory elements, each memory element storing 256 8-bit word segments. Each memory element has address input connections for selectively addressing each word segment and a memory element select connection for enabling the memory element. Each memory element operates in response to a clock pulse at its clock input during a signal at its select connection to read out in parallel the 8 bits of the word segment addressed by signals at the address input connections. Address information bits are received in parallel and applied to a decoding arrangement. The decoding arrangement includes a group of gates which couple a first portion of the address bits to the address input connections of all the memory elements of the system. The decoding arrangement also includes a first decoder coupled to the select connections of all the memory elements of the system for enabling particular memory elements of each array as determined by the second portion of the address bits. A second decoder in the decoding arrangement produces a signal at one of four outputs as determined by a third portion of the address bits. These four outputs are connected to a source of clock pulses and gate a clock pulse to one of the four arrays depending on which output has the signal present. The clock pulse is applied to the clock inputs of all the memory elements of that array.
Inventors
- 👤 J Lighthall
- 👤 H Toy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 03:20
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0653
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
503 words
A memory system comprising several arrays of memory elements, each memory element having the capacity for storing a quantity of word segments, each memory element having word segment address input connections for selectively addressing each word segment of said quantity as determined by signals applied thereto, a number of output connections equal to the number of bits of a word segment, a memory element select connection for enabling the memory element in response to a signal applied thereto, and a clock input connection, each memory element being operable in response to a signal at the clock input connection during a signal at the memory element select connection to read out at the output connections the bits of the word segment addressed by the signals at the address input connections; address receiving means for receiving address information, said address information having a first portion designating a particular one of the word segments of the quantity of word segments in each memory element, a second portion designating a memory element in each array, and a third portion designating an array; decoding means including a first means coupled to said address receiving means and to the address input connections of all the memory elements of the system for applying signals to the address input connections to address a particular word segment of each of the memory elements as designated by the first portion of the address information; said decoding means including a second means coupled to said address receiving means and to the memory element select connectionS of all the memory elements of the system for applying signals to the memory element select connections to enable a particular memory element of each array as designated by the second portion of the address information; said decoding means including a third means coupled to said address receiving means and having a number of output connections equal to the number of arrays of the system, said third means being operable to produce a signal at a particular one of its output connections as determined by the third portion of the address formation; timing means for producing a clock signal during the occurrence of signals from the first, second, and third means of the decoding means; and clock gating means coupled to the output connections of the third means of the decoding means and to the timing means and having a number of output connections equal to the number of arrays, each output connection being connected to the clock input connections of all the memory elements of a different one of the arrays, said clock gating means being operable during a clock signal from the timing means to produce a signal at the clock input connections of all the memory elements of a particular array as designated by the third portion of the address information; whereby the bits of a particular word segment of a particular memory element of a particular array as designated by the address information are read out at the output connection of the particular memory element.
Claim 2
Dependent Claim
503 words
A memory system comprising several arrays of memory elements, each memory element having the capacity for storing a quantity of word segments, each memory element having word segment address input connections for selectively addressing each word segment of said quantity as determined by signals applied thereto, a number of output connections equal to the number of bits of a word segment, a memory element select connection for enabling the memory element in response to a signal applied thereto, and a clock input connection, each memory element being operable in response to a signal at the clock input connection during a signal at the memory element select connection to read out at the output connections the bits of the word segment addressed by the signals at the address input connections; address receiving means for receiving address information, said address information having a first portion designating a particular one of the word segments of the quantity of word segments in each memory element, a second portion designating a memory element in each array, and a third portion designating an array; decoding means including a first means coupled to said address receiving means and to the address input connections of all the memory elements of the system for applying signals to the address input connections to address a particular word segment of each of the memory elements as designated by the first portion of the address information; said decoding means including a second means coupled to said address receiving means and to the memory element select connectionS of all the memory elements of the system for applying signals to the memory element select connections to enable a particular memory element of each array as designated by the second portion of the address information; said decoding means including a third means coupled to said address receiving means and having a number of output connections equal to the number of arrays of the system, said third means being operable to produce a signal at a particular one of its output connections as determined by the third portion of the address formation; timing means for producing a clock signal during the occurrence of signals from the first, second, and third means of the decoding means; and clock gating means coupled to the output connections of the third means of the decoding means and to the timing means and having a number of output connections equal to the number of arrays, each output connection being connected to the clock input connections of all the memory elements of a different one of the arrays, said clock gating means being operable during a clock signal from the timing means to produce a signal at the clock input connections of all the memory elements of a particular array as designated by the third portion of the address information; whereby the bits of a particular word segment of a particular memory element of a particular array as designated by the address information are read out at the output connection of the particular memory element.
Claim 3
Dependent Claim
461 words
A memory system in accordance with claim 1 wherein each memory element has an activating connection and is operable to be switched from an inactive state to an active state in response to a pulse at the activating connection and to be switched from an active state to an inactive state in response to a pulse at the activating connection, said memory element being operable to be read out only while in an active state; said clock gating means has a number of first output connections equal to the number of arrays and a number of associated second output connections equal to the number of arrays, each first output connection being connected to the activating connections of all the memory elements of a different one of the arrays and each second output connection being connected to the clock input connections of all the memory elements of a different one of the arrays, associated first and second output connections being connected to the same arrays; said clock gating means having a number of array select input connections equal to the number of arrays, each array select input connection being connected to a different one of the output connections of the third means of the decoding means; and said clock gating means having first and second clock input connections and being operable during a signal at an array select input connection to produce a pulse at a first output connection in response to a pulse at the first clock input connection and to produce a pulse at the associated second output connection in response to a pulse at the second clock input connection; said timing means has a first output connection connected to the first clock input connection of said clock gating means and a second output connection connected to the second input connection of said clock gating means, said timing means being operable to produce one first clock pulse at its first output connection during the occurrence of a signal from the third means of the decoding means whereby memory elements of a particular array as designated by the third portion of the address information are triggered to the active state, a subsequent second clock pulse at its second output connection during the occurrence of signals from the first, second, and third means of the decoding means whereby the bits of a particular word segment of a particular active memory element of a particular array as designated by the address information are read out at the output connections of the particular memory element, and a subsequent first clock pulse at itS first output connection during the occurrence of a signal from the third means of the decoding means whereby the active memory elements of the array are triggered to the inactive state.
Claim 4
Dependent Claim
258 words
A memory system in accordance with claim 2 wherein each memory element is operable to be switched from the inactive state to the active state in response to a pulse at the activating connection and to be switched from the active state to the inactive state in response to a pulse at the activating connection during the absence of a signal at the memory element select connection; said second means of the decoding means having a control connection and being enabled to produce a signal during a first signal condition applied to the control connection and being inhibited from producing a signal during a second signal condition applied to the control connection; and said timing means being connected to said control connection of the second means of the decoding means and being operable to produce the first signal condition at the control connection during said one first clock pulse and said subsequent second clock pulse and to produce the second signal condition at the control connection during said subsequent first clock pulse, whereby the memory elements of a particular array as designated by the third portion of the address information are activated by said one first clock pulse, the bits of a particular word segment of a particular activated memory element as designated by the address information are read out at the output connections of the particular memory element in response to said subsequent second clock pulse, and the activated memory elements of the particular array are triggered to the inactive state by said subsequent first clock pulse.
Claim 5
Dependent Claim
375 words
A memory system in accordance with claim 3 wherein said address receiving means is a latching means for receiving and storing a plurality of bits representing address information, said latching means having a like plurality of output connections, a first group of output connections being connected to the first means of the decoding means for applying thereto bits designating a particular one of the word segments of the quantity of word segments in each memory element, a second group of output connections being connected to the second means of the decoding means for applying thereto bits designating a particular memory element in each array, and a third group of output connections being connected to the third means of the decoding means for applying thereto bits designating a particular array; said first means of the decoding means includes a number of gates equal to the number of output connections in the first group, each gate being connected to a different one of the output connections and to the word segment address input connections of all the memory elements of the system, said gates being operable to gate bits present on the first group of output connections to the memory elements of the system subsequent to the storing of the bits in the latching means; said second means of the decoding means includes a decoder connected to the second group of output connections of said latching means and to the memory element select connections of the memory elements, said decoder being operable to produce a signal at the memory element select connection of a particular memory element of each array as determined by the combination of bits received from the latching means on the second group of output connections during the first signal condition at said control connections; and said third means of the decoding means includes a decoder connected to the third group of output connections of said latching means and to the output connections of said third means of the decoding means, said decoder being operable to produce a signal at a particular one of the output connections of the third means of the decoding means as determined by the combination of bits received from the latching means on the third grOup of output connections.
Claim 6
Dependent Claim
140 words
A memory system in accordance with claim 4 wherein said timing means includes a train of interconnected monostable multivibrators for producing a set of signals subsequent to the receiving and storing of bits representing address information in said latching means, the set of signals including the first signal condition at the control connection of the second means of the decoding means, said one first clock pulse and said subsequent second clock pulse both during the occurrence of the first signal condition at the control connection of the second means of the decoding means, the second signal condition replacing the first signal condition at the control connection of the second means of the decoding means, and said subsequent first clock pulse during the occurrence of the second signal condition at the control connection of the second means of the decoding means.
References Cited (Backward Citations)
US3771145A
Cited
US3771145B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-12-16 | 1978-06-17 | 1978-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-12-16 | 1982-06-17 | 1982-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-12-16 | 1986-06-17 | 1986-12-17 | $7700.00 | Window Closed / Lapsed |