Spectrally efficient quadrature amplitude modulator

Claim 2

A signal processor comprising: a demultiplexor connected to a serial bit-stream, producing an I bit-stream and a Q bit-stream, said Q bit-stream staggered in time by one-half of a bit interval with respect to said I bit-stream, a first set of latches connected to said I and Q bit-streams, producing first signals representing a current transition state of said I bit-stream along with previous and upcoming transition states of said Q bit-stream, a second set of latches connected to said I and Q bit-streams, producing second signals representing a current transition state of said Q bit-stream along with previous and upcoming transition states of said I bit-stream, a first memory device connected to said first signals representing a current transition state of said I bit-stream along with previous and upcoming transition states of said Q bit-stream, producing an n-bit I digital signal representing a bit transition waveform for said I bit-stream, a second memory device connected to said second signals representing a current transition state of said Q bit-stream along with previous and upcoming transition states of said I bit-stream, producing an n-bit Q digital signal representing a bit transition waveform for said Q bit-stream, a first digital-to-analog converter connected to said I digital signal, producing an analog I signal, a second digital-to-analog converter connected to said Q digital signal, producing an analog Q signal.

Claim 3

A quadrature amplitude modulator comprising a signal processor comprising a demultiplexor coupled to a serial bit stream, producing an I bit-stream and a Q bit-stream, said Q bit-stream staggered in time by one-half of a bit interval with respect to said I bit-stream, a first set of latches coupled to said I and Q bit-streams, producing first signals representing a current transition state of said I bit-stream along with previous and upcoming transition states of said Q bit-stream, a second set of latches coupled to said I and Q bit-streams, producing second signals representing a current transition state of the Q bit-stream along with previous and upcoming transition states of the I bit-stream, a first memory device coupled to said first signals representing a current transition state of said I bit-stream along with previous and upcoming transition states of said Q bit-stream, producing an n-bit I digital signal representing a bit transition waveform for said I bit-stream, a second memory device coupled to said second signals representing a current transition state of said Q bit-stream along with previous and upcoming transition states of said I bit-stream, producing an n-bit Q digital signal representing a bit transition waveform for said Q bit-stream, a first digital-to-analog converter coupled to said I digital signal, producing an analog I signal, a second digital-to-analog converter coupled to said Q digital signal, producing an analog Q signal, a first modulator coupled to a first sinusoidal carrier, having a frequency w o t, and further coupled to said analog I signal, producing a first modulated carrier, a second modulator coupled to a second sinusoidal carrier, having a frequency w o t and offset in phase from said first carrier by 990 degrees, and further coupled to said analog Q signal, producing a second modulated carrier, and a summer coupled to said first and second modulated carriers, producing a quadrature modulated output signal.

Claim 4

A quadrature amplitude modulator comprising a signal processor comprising a demultiplexor coupled to a serial bit stream, producing an I bit-stream and a Q bit-stream, said Q bit-stream staggered in time by one-half of a bit interval with respect to said I bit-stream, a first set of latches coupled to said I and Q bit-streams, producing first signals representing a current transition state of said I bit-stream along with previous and upcoming transition states of said Q bit-stream, a second set of latches coupled to said I and Q bit-streams, producing second signals representing a current transition state of the Q bit-stream along with previous and upcoming transition states of the I bit-stream, a first memory device coupled to said first signals representing a current transition state of said I bit-stream along with previous and upcoming transition states of said Q bit-stream, producing an n-bit I digital signal representing a bit transition waveform for said I bit-stream, a second memory device coupled to said second signals representing a current transition state of said Q bit-stream along with previous and upcoming transition states of said I bit-stream, producing an n-bit Q digital signal representing a bit transition waveform for said Q bit-stream, a first digital-to-analog converter coupled to said I digital signal, producing an analog I signal, a second digital-to-analog converter coupled to said Q digital signal, producing an analog Q signal, a first modulator coupled to a first sinusoidal carrier, having a frequency w o t, and further coupled to said analog I signal, producing a first modulated carrier, a second modulator coupled to a second sinusoidal carrier, having a frequency w o t and offset in phase from said first carrier by 990 degrees, and further coupled to said analog Q signal, producing a second modulated carrier, and a summer coupled to said first and second modulated carriers, producing a quadrature modulated output signal.

Claim 7

A signal processor comprising: a demultiplexer connected to a serial bit-stream, producing an I bit-stream and a Q bit-stream, each of said I and Q bit-streams comprising a plurality of bits having an amplitude normalized to 1, means for staggering said I and Q bit-streams in time with respect to each other by one-half of a bit period, means for selectively suppressing the amplitude of a bit in the I bit-stream to β whenever preceding and succeeding bits in the Q bit-stream have the same value as each other, and means for selectively suppressing the amplitude of a bit in the Q bit-stream to β whenever preceding and succeeding bits in the I bit-stream have the same value as each other.

Claim 8

A signal processor comprising: a demultiplexer connected to a serial bit-stream, producing an I bit-stream and a Q bit-stream, each of said I and Q bit-streams comprising a plurality of bits having an amplitude normalized to 1, means for staggering said I and Q bit-streams in time with respect to each other by one-half of a bit period, means for selectively suppressing the amplitude of a bit in the I bit-stream to β whenever preceding and succeeding bits in the Q bit-stream have the same value as each other, and means for selectively suppressing the amplitude of a bit in the Q bit-stream to β whenever preceding and succeeding bits in the I bit-stream have the same value as each other.

Claim 9

The signal processor of claim 4 further comprising a first bit-shaping means for shaping a bit in the I bit-stream and a second bit-shaping means for shaping a bit in the Q bit-stream.

Claim 10

The signal processor of claim 5 wherein said first bit-shaping means and said second bit-shaping means each provide a bit in the shape of a double-interval raised cosine.

Claim 11

The signal processor of claim 6 wherein β is approximately 0.575.

Claim 12

The signal processor of claim 5 wherein said first bit-shaping means and said second bit-shaping means each provide a bit in the shape of a Blackman window.

Claim 13

The signal processor of claim 8 wherein β is approximately 0.8.

Claim 14

A quadrature amplitude modulator comprising a signal processor comprising a demultiplexor coupled to a serial bit stream, producing an I bit-stream and a Q bit-stream, each of said I and Q bit-streams comprising a plurality of bits having an amplitude normalized to 1, means for staggering said I and Q bit-streams in time with respect to each other by one-half of a bit period, means for selectively suppressing the amplitude of a bit in said I bit-stream to beta whenever preceding and succeeding bits in said Q bit-stream have the same value as each other, means for selectively suppressing the amplitude of a bit in said Q bit-stream to beta whenever preceding and succeeding bits in said I bit-stream have the same value, a first modulator for modulating a first sinusoidal carrier, having a frequency w o t, with said I bit-stream to produce a first modulated carrier, a second modulator for modulating a second sinusoidal carrier, said second carrier having a frequency w o t offset in phase from said first carrier by 90 degrees, with said Q bit-stream to produce a second modulated carrier, and a summer for combining said modulated first and second carriers.

Claim 15

A quadrature amplitude modulator comprising a signal processor comprising a demultiplexor coupled to a serial bit stream, producing an I bit-stream and a Q bit-stream, each of said I and Q bit-streams comprising a plurality of bits having an amplitude normalized to 1, means for staggering said I and Q bit-streams in time with respect to each other by one-half of a bit period, means for selectively suppressing the amplitude of a bit in said I bit-stream to beta whenever preceding and succeeding bits in said Q bit-stream have the same value as each other, means for selectively suppressing the amplitude of a bit in said Q bit-stream to beta whenever preceding and succeeding bits in said I bit-stream have the same value, a first modulator for modulating a first sinusoidal carrier, having a frequency w o t, with said I bit-stream to produce a first modulated carrier, a second modulator for modulating a second sinusoidal carrier, said second carrier having a frequency w o t offset in phase from said first carrier by 90 degrees, with said Q bit-stream to produce a second modulated carrier, and a summer for combining said modulated first and second carriers.

Claim 16

The quadrature amplitude modulator of claim 10, further comprising a first bit-shaping means for shaping the bits in the I bit-stream and second bit-shaping means for shaping the bits in the Q bit-stream.

Claim 17

The quadrature amplitude modulator of claim 11, wherein said first bit-shaping means and said second bit-shaping means each provide a bit in the shape of a double-interval raised cosine.

Claim 18

The quadrature amplitude modulator of claim 12, wherein β is approximately 0.575.

Claim 19

The quadrature amplitude modulator of claim 11, wherein said first bit-shaping means and said second bit-shaping means each provide a bit in the shape of a Blackman window.

Claim 20

The quadrature amplitude modulator of claim 14, wherein β is approximately 0.8.

Claim 21

A spread spectrum transmitter comprising the quadrature amplitude modulator of claim 10, further comprising: a plurality of tables for storing chip sequences, a multiplexer for selecting a plurality of transmission chip sequences from the plurality of tables, and means for combining said plurality of chip sequences into the serial bit-stream to be provided to said quadrature amplitude modulator.

Claim 24

The method of claim 17, further comprising the steps of: shaping the bits of the I bit-stream according to a first bit-shaping function, and shaping the bits of the Q bit-stream according to a second bit-shaping function.

Claim 25

The method of claim 18, wherein said first and second bit-shaping functions each are double-interval raised cosine functions.

Claim 26

The method of claim 18, wherein said first and second bit-shaping functions each are Blackman window functions.