Patent US5544342A successfully refreshed from Google Patents.
US5544342A
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System and method for prefetching information in a processing system
Assignee: International Business Machines Corp
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Filing: 1995-07-10
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Granted: 1996-08-06
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Expires: 2015-07-10
Abstract
Abstract A method and system are provided for prefetching information in a processing system. A first memory has multiple first locations. At least one of the first locations stores information including an address of a different first location, the different first location having been referenced in the first memory after a previous reference to the one first location. A second memory has at least one second location storing information from the one first location, including the address. Information is prefetched to the second memory from the address of the first memory, in response to a reference to the second location.
Inventors
- 👤 Mark E. Dean
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 08:23
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0862; G06F12/0893; G06F12/0897; G06F9/34; G06F9/345; G06F9/3455; G06F9/3824; G06F9/383; G06F9/3832; G06F9/3867; G06F9/3869; G06F2212/00; G06F2212/60; G06F2212/6022; G06F2212/6026
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
162 words
A system for prefetching information in a processing system, comprising: a first memory for storing first and second information; a second memory for selectively storing said first and second information; and circuitry for: determining whether said second memory stores said first information; accessing said first information in said second memory only if said second memory stores said first information, otherwise said first information being accessed in said first memory; determining whether said second memory stores said second information; after accessing said first information, accessing said second information in said second memory only if said second memory stores said second information, otherwise said second information being accessed in said first memory; in response to accessing said second information, modifying said first information in said first memory to include an indication of said second information in said first memory; and in response to accessing said first information, prefetching said second information from said first memory to said second memory ill response to said indication.
Claim 2
Independent Claim
162 words
A system for prefetching information in a processing system, comprising: a first memory for storing first and second information; a second memory for selectively storing said first and second information; and circuitry for: determining whether said second memory stores said first information; accessing said first information in said second memory only if said second memory stores said first information, otherwise said first information being accessed in said first memory; determining whether said second memory stores said second information; after accessing said first information, accessing said second information in said second memory only if said second memory stores said second information, otherwise said second information being accessed in said first memory; in response to accessing said second information, modifying said first information in said first memory to include an indication of said second information in said first memory; and in response to accessing said first information, prefetching said second information from said first memory to said second memory ill response to said indication.
Claim 3
Dependent Claim
42 words
The system of claim 1 wherein said circuitry modifies said first information in said first memory to include said indication in response to said accessing of said second information being a first accessing of information after said accessing of said first information.
Claim 4
Dependent Claim
78 words
The system of claim 1 wherein said circuitry modifies said first information in said first memory to include said indication in response to said accessing of said second information being a second accessing of information after said accessing of said first information, wherein said second accessing results from a miss operation in said second memory, and wherein a first accessing of information after said accessing of said first information results from a prefetch operation in said second memory.
Claim 5
Dependent Claim
14 words
The system of claim 1 wherein said second memory is a zero-level cache memory.
Claim 6
Dependent Claim
15 words
The system of claim 4 wherein said zero-level cache memory is a fully-associative cache memory.
Claim 7
Dependent Claim
16 words
The system of claim 5 wherein said zero-level cache memory is a zero-level data cache memory.
Claim 8
Dependent Claim
15 words
The system of claim 6 wherein said first memory is a first-level data cache memory.
Claim 9
Dependent Claim
21 words
The system of claim 1 and further comprising a processing unit, wherein said second memory is integral with said processing unit.
Claim 10
Dependent Claim
15 words
The system of claim 8 wherein said first memory is integral with said processing unit.
Claim 11
Dependent Claim
25 words
The system of claim 1 wherein said circuitry prefetches said second information in response to an accessing of said first information in said first memory.
Claim 12
Dependent Claim
37 words
The system of claim 10 wherein said circuitry prefetches said second information in response to a cache miss in said second memory, said cache miss resulting in said accessing of said first information in said first memory.
Claim 13
Dependent Claim
16 words
The system of claim 11 wherein said cache miss indicates said accessing of said first information.
Claim 14
Dependent Claim
31 words
The system of claim 1 wherein said circuitry prefetches said second information in response to a cache prefetch operation resulting from an accessing of said first information in said second memory.
Claim 15
Independent Claim
162 words
A method of prefetching information in a processing system, comprising the steps of: storing first and second information in a first memory; selectively storing said first and second information in a second memory; determining whether said second memory stores said first information; accessing said first information in said second memory only if said second memory stores said first information, otherwise said first information being accessed in said first memory; determining whether said second memory stores said second information; after accessing said first information, accessing said second information in said second memory only if said second memory stores said second information, otherwise said second information being accessed in said first memory; in response to accessing said second information, modifying said first information in said first memory to include an indication of said second information in said first memory; and in response to accessing said first information, prefetching said second information from said first memory to said second memory in response to said indication.
Claim 16
Independent Claim
162 words
A method of prefetching information in a processing system, comprising the steps of: storing first and second information in a first memory; selectively storing said first and second information in a second memory; determining whether said second memory stores said first information; accessing said first information in said second memory only if said second memory stores said first information, otherwise said first information being accessed in said first memory; determining whether said second memory stores said second information; after accessing said first information, accessing said second information in said second memory only if said second memory stores said second information, otherwise said second information being accessed in said first memory; in response to accessing said second information, modifying said first information in said first memory to include an indication of said second information in said first memory; and in response to accessing said first information, prefetching said second information from said first memory to said second memory in response to said indication.
Claim 17
Dependent Claim
47 words
The method of claim 14 wherein said modifying step comprises the step of modifying said first information in said first memory to include said indication in response to said accessing of said second information being a first accessing of information after said accessing of said first information.
Claim 18
Dependent Claim
83 words
The method of claim 14 wherein said modifying step comprises the step of modifying said first information in said first memory to include said indication in response to said accessing of said second information being a second accessing of information after said accessing of said first information, wherein said second accessing results from a miss operation in said second memory, and wherein a first accessing of information after said accessing of said first information results from a prefetch operation in said second memory.
Claim 19
Dependent Claim
30 words
The method of claim 14 wherein said prefetching step comprises the step of prefetching said second information in response to an accessing of said first information in said first memory.
Claim 20
Dependent Claim
42 words
The method of claim 17 wherein said prefetching step comprises the step of prefetching said second information in response to a cache miss in said second memory, said cache miss resulting in said accessing of said first information in said first memory.
Claim 21
Dependent Claim
37 words
The method of claim 18 wherein said prefetching step comprises the step of prefetching said second information in response to said cache miss in said second memory, said cache miss indicating said accessing of said first information.
Claim 22
Dependent Claim
36 words
The method of claim 14 wherein said prefetching step comprises the step of prefetching said second information in response to a cache prefetch operation resulting from an accessing of said first information in said second memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-06 | 2000-02-05 | 2000-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-06 | 2004-02-05 | 2004-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-06 | 2008-02-05 | 2008-08-06 | $7700.00 | Window Closed / Lapsed |