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US5544173A
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US
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Delay test coverage without additional dummy latches in a scan-based test design
Assignee: International Business Machines Corp
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Filing: 1995-06-07
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Granted: 1996-08-06
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Expires: 2015-06-07
Abstract
Abstract Scan testing of complex electronic logic circuits for the detection of AC delay faults is improved without the addition of dummy or test-only latches by connecting the shift register latches according to the order determined by the method of first listing all shift register latches in the scan chain with all the combinational circuit outputs traceable from the output; sorting this list in the order of number of outputs controlled, i.e., touched in the forward trace; listing each unique combinational circuit output; sequentially assigning the order of the SRLs in the scan chain so that adjacent SRLs do not control any of the same circuit outputs; when this is not possible assign adjacent SRLs so that the fewest common circuit outputs are controlled by adjacent SRLs or if any remain unassigned, insert an output SRL between adjacent SRLs. The additional consideration of physical distance between SRLs may be added as an ordering criterion.
Inventors
- 👤 David Meltzer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 15:40
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318577; G01R31/31858; G01R31/318583; G01R31/318586
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
225 words
A method of configuring a digital integrated logic circuit having a plurality of interconnected combinational circuits, each having at least one input and at least one output, and a plurality of daisy chained flip-flops arranged as a scan chain of shift register latches, each shift register latch having an output and a scan input, and wherein the output of each of the shift register latches is connected to either an input of one of the plurality interconnected combinational elements or to a primary output of said digital integrated circuit, and is connected to the scan chain input of another shift register latch by a method comprising the steps of: determining the order of connection of said shift register latches in said scan chain to maximize the number of circuits tested for AC delay faults; and in the process assigning a scan chain order by: a. creating a list of all shift register latches (SRLs) in the scan chain with all the combinational circuit outputs traceable from said primary output; b. sorting said list in the order of number of circuit outputs controlled by being touched in a forward trace of said combinational circuits; c. listing each unique combinational circuit output; d. sequentially assigning the order of the SRLs in the scan chain so that adjacent SRLs do not control any of the same circuit outputs.
Claim 2
Independent Claim
225 words
A method of configuring a digital integrated logic circuit having a plurality of interconnected combinational circuits, each having at least one input and at least one output, and a plurality of daisy chained flip-flops arranged as a scan chain of shift register latches, each shift register latch having an output and a scan input, and wherein the output of each of the shift register latches is connected to either an input of one of the plurality interconnected combinational elements or to a primary output of said digital integrated circuit, and is connected to the scan chain input of another shift register latch by a method comprising the steps of: determining the order of connection of said shift register latches in said scan chain to maximize the number of circuits tested for AC delay faults; and in the process assigning a scan chain order by: a. creating a list of all shift register latches (SRLs) in the scan chain with all the combinational circuit outputs traceable from said primary output; b. sorting said list in the order of number of circuit outputs controlled by being touched in a forward trace of said combinational circuits; c. listing each unique combinational circuit output; d. sequentially assigning the order of the SRLs in the scan chain so that adjacent SRLs do not control any of the same circuit outputs.
Claim 3
Dependent Claim
54 words
The method in accordance with claim 1 and further comprising the following steps: when successful assignment according to step d. is not possible, assigning adjacent SRLs so that the fewest common circuit outputs are controlled by adjacent SRLs or if any remain unassigned, then sequentially inserting an output shift register latch between adjacent SRLs.
Claim 4
Dependent Claim
30 words
The method of claim 1 wherein weighted preference is given to assigning adjacent SRLs to the scan chain which are physically closest to each other on the integrated circuit chip.
References Cited (Backward Citations)
US5023875A
Cited
US5187712A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-06 | 2000-02-05 | 2000-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-06 | 2004-02-05 | 2004-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-06 | 2008-02-05 | 2008-08-06 | $7700.00 | Window Closed / Lapsed |