Stackable vertical thin package/plastic molded lead-on-chip memory cube

Claim 2

A semiconductor package comprising; a semiconductor chip having a first major surface with input and output bonding pads thereon, a second major surface substantially parallel to said first major surface and four minor surfaces substantially perpendicular to said major surfaces and joining said major surfaces, a lead frame having a plurality of conductors with distal and proximal ends, the proximal ends of the conductors being positioned adjacent said first major surface of said chip, an insulating layer having a selected thickness positioned between and insulatively bonded to said proximal ends of said conductors and said first major surface, an electrical connection between each respective one of said proximal ends of said conductors and a respective one of each of said bonding pads on the chip, an insulating encapsulation disposed on and substantially enclosing said first major surface, said four minor surfaces, the proximal ends of said conductors and partially enclosing a portion of said distal ends of said conductors, a portion of said distal ends being cantilevered from said encapsulation, and a metallic plate disposed on and in good thermal contact with said second major surface, said plate having a thickness approximately equal to the sum of the thickness of said proximal ends of said lead frame and said insulating layer.

Claim 3

The package of claim 1 wherein said encapsulation extends in thickness past said second major surface to form a recess in said encapsulant around said second major surface, and said plate is disposed in said recess.

Claim 4

The package of claim 1 wherein said distal ends of said conductors in said lead frame extend beyond said insulating layer and are cantilevered therefrom and the thickness of said plate is approximately equal to the thickness of said distal ends of said conductors.

Claim 5

The package of claim 1 wherein said proximal ends of said conductors is one half the thickness of said distal ends.

Claim 6

The package of claim 1 wherein said plate extends past one of said edges of said chip and is thermally coupled to said chip to conduct heat away from said chip.

Claim 7

The package of claim 4 wherein said plate has a thickness approximately equal to the thickness of the distal ends of said conductors.

Claim 8

The package of claim 1 wherein said encapsulation enclosing said first major surface is provided with a plurality of extending hemispheres.

Claim 9

The package of claim 7 wherein said encapsulation encloses at least a portion of second major surface, and is provided with a plurality of sockets that will mate with the extending hemispheres on the encapsulation enclosing the first major surface of any adjacent package.

Claim 10

The package of claim 5 wherein said encapsulation enclosing said first major surface is provided with a small recess to expose a selected portion of a selected one of said lead frame conductors.

Claim 11

The package of claim 1 wherein said encapsulation surrounding at least one of said surfaces is provided with a small recess to expose a selected portion of a selected one of said lead frame conductors.

Claim 12

The package of claim 10 wherein said encapsulation encloses at least a portion of said second major surface, said encapsulation on said second major surface including a small recess, and said plate is provided with an opening therein which aligns with said small recess on said second major surface, said opening being larger than said small recess.

Claim 13

The package of claim 10 wherein a capacitor resides in said recess and is coupled to said selected one of said lead frame conductors.

Claim 14

The package of claim 11 wherein a capacitor resides in said recess and is coupled to said selected one of said lead frame conductors.

Claim 15

A vertical thin package comprising: an integrated circuit having an active side, a substantially planar back side, and four edges; a lead frame electrically connected to said front side of said chip, said lead frame terminating in a plurality of lead ends; a molded package encasing (1) said active side and said four edges of said chip, with said back side exposed, and (2) all of said lead frame except said plurality of lead ends, said package having a peripheral edge and a substantially planar first surface that is substantially coplanar with said back side of said chip; a conductive plate thermally attached to said back side of said chip to conduct heat away from said chip via said plate, said plate extending past said peripheral edge of said package and having a substantially uniform thickness over its entire area; and wherein said chip, said lead frame, said molded package and said metallic plate are designed and constructed so that said package has an overall thickness of no more than about 1.27 mm.

Claim 16

A vertical thin package comprising: an integrated circuit having an active side, a substantially planar back side, and four edges; a lead frame electrically connected to said front side of said chip, said lead frame terminating in a plurality of lead ends; a molded package encasing (1) said active side and said four edges of said chip, with said back side exposed, and (2) all of said lead frame except said plurality of lead ends, said package having a peripheral edge and a substantially planar first surface that is substantially coplanar with said back side of said chip; a conductive plate thermally attached to said back side of said chip to conduct heat away from said chip via said plate, said plate extending past said peripheral edge of said package and having a substantially uniform thickness over its entire area; and wherein said chip, said lead frame, said molded package and said metallic plate are designed and constructed so that said package has an overall thickness of no more than about 1.27 mm.

Claim 17

The package of claim 14 wherein said package includes; an insulating layer having a selected thickness positioned between and insulatively bonded to said encapsulated portions of said lead frame and said active side, said lead ends of said lead frame extending beyond said molded package and cantilevered therefrom.

Claim 18

A stack of semiconductor chip packages comprising; a plurality of semiconductor chip packages, each chip package comprising; a semiconductor chip having a first major surface with input and output bonding pads thereon, a second major surface substantially parallel to said first major surface and four minor surfaces substantially perpendicular to said major surfaces and joining said major surfaces, a lead frame having a plurality of conductors with distal and proximal ends, the proximal ends of the conductors being positioned adjacent said first major surface of said chip, an electrical connection between each respective one of said proximal ends of said conductors and a respective one of each of said bonding pads on the chip, an insulating layer having a selected thickness positioned between and insulatively bonded to said proximal ends of said conductors and said first major surface, an insulating encapsulation disposed on and substantially enclosing said first major surface, said four minor surfaces, the proximal ends of said conductors and partially enclosing a portion of said distal ends of said conductors, a portion of said distal ends being cantilevered from said encapsulation, a metallic plate disposed on and in good thermal contact with said second major surface, and said plate having a thickness substantially equal to the sum of the thickness of said proximal ends of said lead frame and the thickness of said insulating layer, each semiconductor chip package, in said stack, having an adhesive layer disposed on the encapsulation disposed over any said first major surface positioned adjacent the metallic plate on an adjacent chip package.

Claim 19

A stack of semiconductor chip packages comprising; a plurality of semiconductor chip packages, each chip package comprising; a semiconductor chip having a first major surface with input and output bonding pads thereon, a second major surface substantially parallel to said first major surface and four minor surfaces substantially perpendicular to said major surfaces and joining said major surfaces, a lead frame having a plurality of conductors with distal and proximal ends, the proximal ends of the conductors being positioned adjacent said first major surface of said chip, an electrical connection between each respective one of said proximal ends of said conductors and a respective one of each of said bonding pads on the chip, an insulating layer having a selected thickness positioned between and insulatively bonded to said proximal ends of said conductors and said first major surface, an insulating encapsulation disposed on and substantially enclosing said first major surface, said four minor surfaces, the proximal ends of said conductors and partially enclosing a portion of said distal ends of said conductors, a portion of said distal ends being cantilevered from said encapsulation, a metallic plate disposed on and in good thermal contact with said second major surface, and said plate having a thickness substantially equal to the sum of the thickness of said proximal ends of said lead frame and the thickness of said insulating layer, each semiconductor chip package, in said stack, having an adhesive layer disposed on the encapsulation disposed over any said first major surface positioned adjacent the metallic plate on an adjacent chip package.

Claim 20

The stack of claim 16 wherein each package is further provided with said distal ends of said conductors in said lead frame extending beyond said insulating layer and cantilevered therefrom, and said proximal ends of said conductors is one half the thickness of said distal ends.

Claim 21

The stack of claim 16 wherein each plate affixed to a respective one of said packages extends out of said stack to conduct heat away from said stack.

Claim 22

The stack of claim 16 wherein each of said packages has in its encapsulation, on said first major side, a plurality of extending hemispheres and on said second major surface a plurality of sockets that will align with the extending hemispheres on the first major side on any adjacent package.

Claim 23

The stack of claim 16 wherein each of said packages is provided with a capacitor coupled to a selected one of said lead frame conductors in said package.

Claim 24

A stack of semiconductor chip packages comprising: a plurality of semiconductor chip packages, each comprising: an integrated circuit having an active side, a substantially planar back side, and four edges; a lead frame electrically connected to said front side of said chip, said lead frame terminating in a plurality of lead ends; a molded package encasing (1) said active side and said four edges of said chip, with said back side exposed, and (2) all of said lead frame except said plurality of lead ends, said package having a peripheral edge and a substantially planar first surface that is substantially coplanar with said back side of said chip; a conductive plate attached to said back side of said chip in a manner permitting heat to be conducted away from said chip via said plate, said plate extending past said peripheral edge of said package and having a substantially uniform thickness over its entire area; and said chip, said lead frame, said molded package and said metallic plate have an overall thickness of no more than about 1.27 mm.

Claim 25

A stack of semiconductor chip packages comprising: a plurality of semiconductor chip packages, each comprising: an integrated circuit having an active side, a substantially planar back side, and four edges; a lead frame electrically connected to said front side of said chip, said lead frame terminating in a plurality of lead ends; a molded package encasing (1) said active side and said four edges of said chip, with said back side exposed, and (2) all of said lead frame except said plurality of lead ends, said package having a peripheral edge and a substantially planar first surface that is substantially coplanar with said back side of said chip; a conductive plate attached to said back side of said chip in a manner permitting heat to be conducted away from said chip via said plate, said plate extending past said peripheral edge of said package and having a substantially uniform thickness over its entire area; and said chip, said lead frame, said molded package and said metallic plate have an overall thickness of no more than about 1.27 mm.

Claim 26

The stack of claim 21 wherein each said package further includes; an insulating layer having a selected thickness positioned between and insulatively bonded to said encapsulated portions of said lead frame and said active side, and said lead ends of said lead frame extend beyond said molded package and are cantilevered therefrom.

Claim 27

A stack of semiconductor chip packages comprising; a plurality of substantially planar semiconductor packages having front surfaces and back surfaces, the front surface of each of said chip packages being bonded to the back surface of any adjacent chip package in said stack by a layer a thermoplastic polyimide adhesive, each of said chip packages comprising: an integrated circuit having an active side, a substantially planar back side, and four edges; a lead frame electrically connected to said front side of said chip, said lead frame terminating in a plurality of lead ends; a molded package encasing (1) said active side and said four edges of said chip, with said back side of said chip exposed, and (2) all of said lead frame except said plurality of lead ends, said package having a peripheral edge and a substantially planar first surface that is substantially coplanar with said back side of said chip; a conductive plate attached to said back side of said chip in a manner permitting heat to be conducted away from said chip via said plate, said plate extending past said peripheral edge of said package and having a substantially uniform thickness over its entire area; and said thermoplastic adhesive has a bonding temperature of about 230 degrees Celsius.

Claim 28

A stack of semiconductor chip packages comprising; a plurality of substantially planar semiconductor packages having front surfaces and back surfaces, the front surface of each of said chip packages being bonded to the back surface of any adjacent chip package in said stack by a layer a thermoplastic polyimide adhesive, each of said chip packages comprising: an integrated circuit having an active side, a substantially planar back side, and four edges; a lead frame electrically connected to said front side of said chip, said lead frame terminating in a plurality of lead ends; a molded package encasing (1) said active side and said four edges of said chip, with said back side of said chip exposed, and (2) all of said lead frame except said plurality of lead ends, said package having a peripheral edge and a substantially planar first surface that is substantially coplanar with said back side of said chip; a conductive plate attached to said back side of said chip in a manner permitting heat to be conducted away from said chip via said plate, said plate extending past said peripheral edge of said package and having a substantially uniform thickness over its entire area; and said thermoplastic adhesive has a bonding temperature of about 230 degrees Celsius.

Claim 29

The stack of claim 23 wherein said thermoplastic adhesive has a delamination temperature of 210 degree Celsius.