Forward overvoltage protection circuit for a vertical semiconductor component

Claim 2

A VDMOS or IGBT-type power transistor, comprising: a plurality of identical active cells formed in an upper surface of a semiconductor substrate doped with a first conductivity type, each active cell including: a low doped well region of a second conductivity type and having a deeper and more highly doped central portion; source diffusion regions substantially peripheral to and within the low doped well region and having a highly doped level of the first conductivity type, the source diffusion regions thereby forming peripheral regions within the low doped well region; a second electrode contacting an upper surface of the central portion of the low doped well region and the source diffusion regions; a control electrode disposed on top of an insulating layer which is disposed over the peripheral regions; end a first main electrode formed on a lower surface of the substrate; and at least one additional cell manufactured according to the same steps as the active cells and disposed in parallel between the first main electrode and the control electrode, the at least one additional cell having a smaller lateral sized low doped well region than the identical cells such that the at least one additional cell has an avalanche threshold lower than an avalanche threshold of the plurality of identical active cells.

Claim 3

A power transistor, comprising: a plurality of identical cells formed in an upper surface of a semiconductor substrate doped with a first conductivity type, each identical cell including: a low doped well region of a second conductivity type, the low doped well region having a deeper and more highly doped central portion; source diffusion regions substantially peripheral to and within the low doped well region and having a highly doped level of the first conductivity type, the source diffusion regions thereby defining a peripheral region within the low doped well region; a second electrode contacting an upper surface of the central portion of the low doped well region and the source diffusion regions; a control electrode disposed on top of an insulating layer which is formed over the peripheral region of the low doped well region; and a first main electrode formed on a lower surface of the semiconductor substrate; at least one additional cell formed in the upper surface of the semiconductor substrate, the additional cell including: a main electrode formed on the lower surface of the semiconductor substrate and coupled to the main electrode of the plurality of identical cells; a low doped well region of a second conductivity type, the low doped well region having a deeper and more highly doped central portion and having a smaller area than the low doped well region of the plurality of identical cells; a second electrode formed on an upper surface of the central portion of the low doped well region of the additional cell and which is coupled to the control electrode of the plurality of identical cells; and a control electrode disposed on top of an insulating layer formed over a peripheral region of the low doped well region of the additional cell.

Claim 4

A power transistor, comprising: a plurality of identical cells formed in an upper surface of a semiconductor substrate doped with a first conductivity type, each identical cell including: a low doped well region of a second conductivity type, the low doped well region having a deeper and more highly doped central portion; source diffusion regions substantially peripheral to and within the low doped well region and having a highly doped level of the first conductivity type, the source diffusion regions thereby defining a peripheral region within the low doped well region; a second electrode contacting an upper surface of the central portion of the low doped well region and the source diffusion regions; a control electrode disposed on top of an insulating layer which is formed over the peripheral region of the low doped well region; and a first main electrode formed on a lower surface of the semiconductor substrate; at least one additional cell formed in the upper surface of the semiconductor substrate, the additional cell including: a main electrode formed on the lower surface of the semiconductor substrate and coupled to the main electrode of the plurality of identical cells; a low doped well region of a second conductivity type, the low doped well region having a deeper and more highly doped central portion and having a smaller area than the low doped well region of the plurality of identical cells; a second electrode formed on an upper surface of the central portion of the low doped well region of the additional cell and which is coupled to the control electrode of the plurality of identical cells; and a control electrode disposed on top of an insulating layer formed over a peripheral region of the low doped well region of the additional cell.

Claim 5

The VDMOS or IGBT-type power transistor as claimed in claim 1, wherein the at least one additional cell is turned on, in response to a voltage across the first main electrode and the second main electrode of the plurality of identical active cells, before the plurality of identical active cells reach an avalanche threshold.

Claim 6

The power transistor as claimed in claim 2, wherein the at least one additional cell is turned on, in response to a voltage across the first main electrode and the second main electrode of the plurality of identical cells, before the plurality of identical cells reach an avalanche threshold.

Claim 7

The power transistor as claimed in claim 2, wherein the at least one additional cell has an avalanche threshold lower than an avalanche threshold of the plurality of identical cells.