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US5541874A
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Semiconductor-integrated-circuit SRAM-cell array with single-ended current-sensing
Assignee: AT&T Inc
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Filing: 1995-09-01
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Granted: 1996-07-30
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Expires: 2015-09-01
Abstract
Abstract Each memory cell in an SRAM array contains an auxiliary reading transistor connected across one of the transistors in each cell. A row read line controls the ON-OFF condition of this auxiliary reading transistor. In addition, each cell has two access transistors for connecting the cell to complementary column bit lines The ON-OFF condition of both of these access transistors is controlled by a row write line. Each cell has two power nodes, one connected to a power source such as VDD and the other connected to a column detector line that terminates in a current sensor. The state of the memory cell is sensed by this current sensor. In one embodiment, the power line that brings the voltage VDD to the cells is a column line; in another embodiment, it is a row line. Thus there are a total of four column lines and two row lines in the one embodiment, and a total of three column lines and three row lines in the other embodiment.
Inventors
- 👤 Kevin J. O'Connor
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 10:39
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C8/00; G11C8/16; G11C11/413; G11C11/417
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
325 words
Semiconductor integrated circuitry comprising: (a) a row-column array including a plurality of SRAM cells integrated in a semiconductor body, each of the cells having a separate first power terminal, a separate detector terminal, and ,separate first and second access transistors, each of the access transistors having a pair of high current carrying terminals and a control terminal, the plurality including first and second SRAM cells located at an intersection of first and second rows, respectively, with a first column; (b) first and second electrically conductive column lines located adjacent to the first column, a first and a second output terminal of each of the first and second SRAM cells being connected to the first and second column lines, respectively, through the high current carrying terminals of the first and second access transistors, respectively, of the first and second cells, respectively; (c) a first pair of electrically conductive row lines located adjacent to the first row, and a second pair of electrically conductive row lines located adjacent to the second row; (d) first and second electrical conductors connecting one of the row lines of the first and second pairs of row lines to the control terminals of both of the access transistors of the first and second cells, respectively; (e) a power line connected to the power terminal of both of the cells; (f) first and second auxiliary transistors located in the first and second cells, respectively, and having a control terminal that is separately connected to the other row line of the first and second pairs, respectively, and having first and second high current carrying terminals respectively connected to the power line and to the first output terminal of the first and second cells, respectively; and (g) a current sensing device having a pair of terminals, one of which is connected to each of the detector terminals of the plurality of the cells and the other of which is connected to a second power terminal.
Claim 2
Dependent Claim
325 words
Semiconductor integrated circuitry comprising: (a) a row-column array including a plurality of SRAM cells integrated in a semiconductor body, each of the cells having a separate first power terminal, a separate detector terminal, and ,separate first and second access transistors, each of the access transistors having a pair of high current carrying terminals and a control terminal, the plurality including first and second SRAM cells located at an intersection of first and second rows, respectively, with a first column; (b) first and second electrically conductive column lines located adjacent to the first column, a first and a second output terminal of each of the first and second SRAM cells being connected to the first and second column lines, respectively, through the high current carrying terminals of the first and second access transistors, respectively, of the first and second cells, respectively; (c) a first pair of electrically conductive row lines located adjacent to the first row, and a second pair of electrically conductive row lines located adjacent to the second row; (d) first and second electrical conductors connecting one of the row lines of the first and second pairs of row lines to the control terminals of both of the access transistors of the first and second cells, respectively; (e) a power line connected to the power terminal of both of the cells; (f) first and second auxiliary transistors located in the first and second cells, respectively, and having a control terminal that is separately connected to the other row line of the first and second pairs, respectively, and having first and second high current carrying terminals respectively connected to the power line and to the first output terminal of the first and second cells, respectively; and (g) a current sensing device having a pair of terminals, one of which is connected to each of the detector terminals of the plurality of the cells and the other of which is connected to a second power terminal.
Claim 3
Dependent Claim
29 words
Circuitry according to claim 1 in which each of the cells comprises a pair of cross-coupled transistor drivers that are separately connected in series with a separate load device.
Claim 4
Dependent Claim
20 words
Circuitry according to claim 1 in which the power line runs essentially parallel to the first and second column lines.
Claim 5
Dependent Claim
17 words
Circuitry according to claim 3 further comprising a current sensing device connected to the second power line.
Claim 6
Dependent Claim
29 words
Circuitry according to claim 4 in which each of the cells comprises a pair of cross-coupled transistor drivers that are separately connected in series with a separate load device.
Claim 7
Dependent Claim
29 words
Circuitry according to claim 4 in which each of the cells comprises a pair of cross-coupled n-channel transistors separately connected in series with a pair of cross-coupled p-channel transistors.
Claim 8
Dependent Claim
45 words
Circuitry according to claim 6 in which the n-channel transistors are NMOS transistors, the p-channel transistors are PMOS transistors, the auxiliary transistor is an NMOS transistor, and the first power terminal is connected to a high current carrying terminal of both of the PMOS transistors.
Claim 9
Dependent Claim
15 words
Circuitry according to claim 7 further comprising a power source connected to the power line.
Claim 10
Dependent Claim
15 words
Circuitry according to claim 6 further comprising a power source connected to the power line.
Claim 11
Dependent Claim
15 words
Circuitry according to claim 5 further comprising a power source connected to the power line.
Claim 12
Dependent Claim
15 words
Circuitry according to claim 4 further comprising a power source connected to the power line.
Claim 13
Dependent Claim
15 words
Circuitry according to claim 3 further comprising a power source connected to the power line.
Claim 14
Dependent Claim
17 words
Circuitry according to claim 1 or 2 further comprising a power source connected to the power line.
Claim 15
Dependent Claim
25 words
Circuitry according to claim 1 or 2 in which between the first and second cells the power line runs essentially parallel to the row lines.
Claim 16
Dependent Claim
15 words
Circuitry according to claim 14 further comprising a power source connected to the power line.
Claim 17
Dependent Claim
20 words
Circuitry according to claim 1 in which the detector line runs, within the array, essentially parallel to the row lines.
Claim 18
Dependent Claim
17 words
Circuitry according to claim 16 further comprising a current sensing device connected to the second power line.
References Cited (Backward Citations)
US5321658A
Cited
US5282174A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-30 | 2000-01-29 | 2000-07-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-30 | 2004-01-29 | 2004-07-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-30 | 2008-01-29 | 2008-07-30 | $7700.00 | Window Closed / Lapsed |