US5282174A
Expired / Lapsed
US
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Dual-port memory with read and read/write ports
Assignee: Nokia Bell Labs
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Filing: 1992-01-31
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Granted: 1994-01-25
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Expires: 2012-01-31
Abstract
Abstract A dual-port memory is accessed via a fast read port through p-channel access transistors and via a slow read/write port through n-channel access transistors. To reduce the disturbances resulting from a read operation through the read/write port, the row-line voltage applied to the gates of the n-channel access transistors is reduced to a value (e.g., 3 volts) below the value used for a write operation (e.g., 5 volts). In this manner, the lowered conductance of the n-channel access transistors during a read operation minimizes the effects of the pre-charged column conductors on the memory cell. Problems that could occur with a simultaneous read from the fast port, among others, are reduced.
Inventors
- 👤 Trevor E. Little
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 10:33
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/16; G11C5/00; G11C5/14; G11C5/147
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
138 words
An integrated circuit comprising a memory cell that may be accessed through a read port and through a read/write port, wherein said memory cell is powered by a first power supply voltage and a second power supply voltage; characterized in that integrated circuit further comprises: at least one access transistor of a given conductivity that couples said read port to said memory cell; at least one access transistor of the opposite conductivity that couples said read/write port to said memory cell; and means for generating a multi-level row-line voltage that is applied to the control electrode of the access transistor that couples said read/write port to said memory cell, wherein a high voltage level is applied during a write operation, and a lower voltage level less than said second power supply level is applied during a read operation.
Claim 2
Dependent Claim
138 words
An integrated circuit comprising a memory cell that may be accessed through a read port and through a read/write port, wherein said memory cell is powered by a first power supply voltage and a second power supply voltage; characterized in that integrated circuit further comprises: at least one access transistor of a given conductivity that couples said read port to said memory cell; at least one access transistor of the opposite conductivity that couples said read/write port to said memory cell; and means for generating a multi-level row-line voltage that is applied to the control electrode of the access transistor that couples said read/write port to said memory cell, wherein a high voltage level is applied during a write operation, and a lower voltage level less than said second power supply level is applied during a read operation.
Claim 3
Dependent Claim
25 words
The integrated circuit of claim 1 wherein said lower voltage level is in the range of from 0.3 to 0.8 of said high voltage level.
Claim 4
Dependent Claim
22 words
The integrated circuit of claim 1 wherein said lower voltage level is a transistor threshold voltage drop below said high voltage level.
Claim 5
Dependent Claim
56 words
The integrated circuit of claim 1 wherein said access transistor of a given conductivity is a p-channel field effect transistor, said access transistor of the opposite conductivity is an n-channel field effect transistor, and said second power supply voltage (e.g., V DD ) is more positive than said first power supply voltage (e.g., V SS ).
Claim 6
Dependent Claim
157 words
An integrated circuit comprising a memory cell that may be accessed through a read port and through a read/write port, wherein said memory cell is powered by a first power supply voltage and a second power supply voltage; characterized in that integrated circuit further comprises: at least one access transistor of a given conductivity that couples said read port to said memory cell; at least one access transistor of the opposite conductivity that couples said read/write port to said memory cell; and means for generating a multi-level row-line voltage that is applied to the gate of the access transistor that couples said read/write port to said memory cell, wherein a high voltage level substantially equal to said second power supply voltage is applied during a write operation, and a lower voltage level is applied during a read operation, wherein said lower voltage level is in the range of from 0.3 to 0.8 of said high voltage level.
Claim 7
Dependent Claim
157 words
An integrated circuit comprising a memory cell that may be accessed through a read port and through a read/write port, wherein said memory cell is powered by a first power supply voltage and a second power supply voltage; characterized in that integrated circuit further comprises: at least one access transistor of a given conductivity that couples said read port to said memory cell; at least one access transistor of the opposite conductivity that couples said read/write port to said memory cell; and means for generating a multi-level row-line voltage that is applied to the gate of the access transistor that couples said read/write port to said memory cell, wherein a high voltage level substantially equal to said second power supply voltage is applied during a write operation, and a lower voltage level is applied during a read operation, wherein said lower voltage level is in the range of from 0.3 to 0.8 of said high voltage level.
Claim 8
Dependent Claim
52 words
The integrated circuit of claim 5 wherein said access transistor of a given conductivity is a p-channel transistor, said access transistor of the opposite conductivity is an n-channel transistor, and said second power supply voltage (e.g., V DD ) is more positive than said first power supply voltage (e.g., V SS ).
Claim 9
Dependent Claim
154 words
An integrated circuit comprising a memory cell that may be accessed through a read port and through a read/write port, wherein said memory cell is powered by a first power supply voltage and a second power supply voltage; characterized in that integrated circuit further comprises: at least one access transistor of a given conductivity that couples said read port to said memory cell; at least one access transistor of the opposite conductivity that couples said read/write port to said memory cell; and means for generating a multi-level row-line voltage that is applied to the gate of the access transistor that couples said read/write port to said memory cell, wherein a high voltage level substantially equal to said second power supply voltage is applied during a write operation, and a lower voltage level is applied during a read operation, wherein said lower voltage level is a transistor threshold voltage drop below said high voltage level.
Claim 10
Dependent Claim
154 words
An integrated circuit comprising a memory cell that may be accessed through a read port and through a read/write port, wherein said memory cell is powered by a first power supply voltage and a second power supply voltage; characterized in that integrated circuit further comprises: at least one access transistor of a given conductivity that couples said read port to said memory cell; at least one access transistor of the opposite conductivity that couples said read/write port to said memory cell; and means for generating a multi-level row-line voltage that is applied to the gate of the access transistor that couples said read/write port to said memory cell, wherein a high voltage level substantially equal to said second power supply voltage is applied during a write operation, and a lower voltage level is applied during a read operation, wherein said lower voltage level is a transistor threshold voltage drop below said high voltage level.
Claim 11
Dependent Claim
52 words
The integrated circuit of claim 7 wherein said access transistor of a given conductivity is a p-channel transistor, said access transistor of the opposite conductivity is an n-channel transistor, and said second power supply voltage (e.g., V DD ) is more positive than said first power supply voltage (e.g., V SS ).
Claim 12
Dependent Claim
148 words
The integrated circuit of claim 8 wherein said means for generating a multi-level row-line voltage comprises: first, second, and third n-channel transistors (202, 204, 205) having source and drain regions serially connected between a positive power supply voltage (V DD ) and a negative power supply voltage (V SS ), with an output node (206) formed at the connection of said first and second transistors; a p-channel transistor (203) having a source connected to said positive power supply voltage and a drain connected to said output node; an inverter (201) having an output connected to the gate of said first n-channel transistor; a first control signal line (DRV3VOLT) connected to the input of said inverter and to the gate of said second n-channel transistor; and a second control signal line (DRV5VOLT) connected to the gate of said third n-channel transistor and to the gate of said p-channel transistor.
Claim 13
Dependent Claim
38 words
The integrated circuit of claim 9 further comprising a multiplicity of complementary inverters (207-208, 209-210) connected to said output node (206) for distributing the output voltage at said output node to a multiplicity of row-line conductors (ROWLINE0, ROWLINE1).
References Cited (Backward Citations)
US5016214A
Cited
US5036491A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-24 | 1997-07-26 | 1998-01-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-24 | 2001-07-26 | 2002-01-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-24 | 2005-07-26 | 2006-01-25 | $7700.00 | Window Closed / Lapsed |