US5541137A
Expired / Lapsed
US
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Method of forming improved contacts from polysilicon to silicon or other polysilicon layers
Assignee: Micron Technology Inc
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Filing: 1994-10-27
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Granted: 1996-07-30
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Expires: 2014-10-27
Abstract
Abstract The method of the present invention introduces a method of forming conductively doped contacts on a supporting substrate in a semiconductor device that minimizes the lateral out-diffusion of the conductive dopants and also provides for a low resistive contact by the steps of: preparing a conductive area to accept contact formation; forming a phosphorus insitu doped polysilicon layer over the conductive area; forming an arsenic insitu doped polysilicon layer over the phosphorus insitu doped polysilicon layer, wherein the two insitu doped polysilicon layers are deposited one after another in separate deposition steps; and annealing the layers at a temperature range of approximately 900°-1100° C. thereby, resulting in sufficient thermal treatment to allow phosphorus atoms to break up a first interfacial silicon dioxide layer formed between the conductive area and the phosphorus insitu doped polysilicon layer.
Inventors
- 👤 Monte Manning
- 👤 Shubneesh Batra
- 👤 Charles H. Dennison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:12
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; Y; Y10; Y10S; Y10S148/00; Y10S148/038; Y10S148/123
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
158 words
A method of forming conductively doped contacts on a supporting substrate in a semiconductor device, said method comprising the steps of: preparing a conductive area to accept contact formation; forming a phosphorus doped polysilicon layer over said conductive area, said conductive area and said phosphorus layer having a first interfacial silicon dioxide layer therebetween; forming an arsenic doped polysilicon layer over said phosphorus doped polysilicon layer that is at least five times greater in thickness than said phosphorus doped polysilicon layer, said arsenic doped polysilicon layer and said phosphorus doped polysilicon layer having a second interfacial silicon dioxide layer therebetween; annealing said layers to provide sufficient thermal treatment to allow phosphorus atoms to break up said first interfacial silicon dioxide layer while said second interfacial silicon dioxide layer deters the out-diffusion of phosphorus atoms into said arsenic doped polysilicon layer; and further annealing said layers so that said phosphorus atoms break up said second interfacial silicon dioxide layer.
Claim 2
Independent Claim
158 words
A method of forming conductively doped contacts on a supporting substrate in a semiconductor device, said method comprising the steps of: preparing a conductive area to accept contact formation; forming a phosphorus doped polysilicon layer over said conductive area, said conductive area and said phosphorus layer having a first interfacial silicon dioxide layer therebetween; forming an arsenic doped polysilicon layer over said phosphorus doped polysilicon layer that is at least five times greater in thickness than said phosphorus doped polysilicon layer, said arsenic doped polysilicon layer and said phosphorus doped polysilicon layer having a second interfacial silicon dioxide layer therebetween; annealing said layers to provide sufficient thermal treatment to allow phosphorus atoms to break up said first interfacial silicon dioxide layer while said second interfacial silicon dioxide layer deters the out-diffusion of phosphorus atoms into said arsenic doped polysilicon layer; and further annealing said layers so that said phosphorus atoms break up said second interfacial silicon dioxide layer.
Claim 3
Dependent Claim
15 words
The method as recited in claim 1, wherein said supporting substrate comprises a silicon substrate.
Claim 4
Dependent Claim
20 words
The method as recited in claim 1, wherein said conductive area is a conductively doped portion of a silicon substrate.
Claim 5
Dependent Claim
27 words
The method as recited in claim 1, wherein said phosphorus doped polysilicon layer is doped with a concentration of phosphorus impurities greater than 5E19 cm -3 .
Claim 6
Dependent Claim
17 words
The method as recited in claim 1, wherein said conductive area is a conductively doped polysilicon material.
Claim 7
Dependent Claim
31 words
The method as recited in claim 1, wherein the two doped polysilicon layers are deposited one after another in separate deposition steps, thereby forming said second interfacial silicon dioxide layer therebetween.
Claim 8
Dependent Claim
71 words
The method as recited in claim 6, wherein the presence of said second interfacial silicon dioxide layer initially hinders the out-diffusion of said phosphorus atoms into said overlying arsenic doped polysilicon layer to thereby provide sufficient time for the phosphorus atoms to breakup said first interfacial silicon dioxide layer duringwhich the phosphorus atoms also break up said second interfacial silicon dioxide layer prior to out-diffusing into said arsenic doped polysilicon layer.
Claim 9
Dependent Claim
37 words
The method as recited in claim 1, wherein said phosphorus doped polysilicon layer has a thickness in the range of 100-500 Å and said arsenic doped polysilicon layer has a thickness in the range of 500-5000 Å.
Claim 10
Dependent Claim
21 words
The method as recited in claim 1, wherein said annealing step is performed at a temperature range of approximately 900°-1100° C.
Claim 11
Dependent Claim
14 words
The method as recited in claim 1, wherein said semiconductor device comprises memory devices.
Claim 12
Dependent Claim
39 words
The method as recited in claim 1, wherein said annealing step is performed such that the arsenic atoms and the phosphorus atoms diffuse into the conductive area no more than 500-1000 Å from the edge of said contact formation.
Claim 13
Dependent Claim
16 words
The method as recited in claim 1, wherein the two doped polysilicon layers are insitu doped.
Claim 14
Dependent Claim
17 words
The method as recited in claim 1, wherein the two doped polysilicon layers are doped by implantation.
Claim 15
Independent Claim
182 words
A method of forming conductively doped contacts on a supporting substrate in a semiconductor device, said method comprising the steps of: preparing a conductive area to accept contact formation; forming a phosphorus insitu doped polysilicon layer over said conductive area, said conductive area and said phosphorus insitu doped polysilicon layer having a first interfacial silicon dioxide layer therebetween; forming an arsenic insitu doped polysilicon layer over said phosphorus insitu doped polysilicon layer that is at least five times greater in thickness than said phosphorus doped polysilicon layer, said arsenic insitu doped polysilicon layer and said phosphorus insitu doped polysilicon layer having a second interfacial silicon dioxide layer therebetween and where the two insitu doped polysilicon layers are deposited one after another in separate deposition steps; annealing said layers to provide sufficient thermal treatment to allow phosphorus atoms to break up said first interfacial silicon dioxide layer while said second interfacial silicon dioxide layer deters the out-diffusion of phosphorus atoms into said second polysilicon layer; and further annealing said layers so that said phosphorus atoms break up said second interfacial silicon dioxide layer.
Claim 16
Independent Claim
182 words
A method of forming conductively doped contacts on a supporting substrate in a semiconductor device, said method comprising the steps of: preparing a conductive area to accept contact formation; forming a phosphorus insitu doped polysilicon layer over said conductive area, said conductive area and said phosphorus insitu doped polysilicon layer having a first interfacial silicon dioxide layer therebetween; forming an arsenic insitu doped polysilicon layer over said phosphorus insitu doped polysilicon layer that is at least five times greater in thickness than said phosphorus doped polysilicon layer, said arsenic insitu doped polysilicon layer and said phosphorus insitu doped polysilicon layer having a second interfacial silicon dioxide layer therebetween and where the two insitu doped polysilicon layers are deposited one after another in separate deposition steps; annealing said layers to provide sufficient thermal treatment to allow phosphorus atoms to break up said first interfacial silicon dioxide layer while said second interfacial silicon dioxide layer deters the out-diffusion of phosphorus atoms into said second polysilicon layer; and further annealing said layers so that said phosphorus atoms break up said second interfacial silicon dioxide layer.
Claim 17
Dependent Claim
26 words
The method as recited in claim 14, wherein said phosphorus doped polysilicon layer is doped with a concentration of phosphorus greater than 5E19 cm -3 .
Claim 18
Dependent Claim
15 words
The method as recited in claim 14, wherein said supporting substrate comprises a silicon substrate.
Claim 19
Dependent Claim
20 words
The method as recited in claim 14, wherein said conductive area is a conductively doped portion of a silicon substrate.
Claim 20
Dependent Claim
17 words
The method as recited in claim 14, wherein said conductive area is a conductively doped polysilicon material.
Claim 21
Dependent Claim
73 words
The method as recited in claim 14, wherein the presence of said second interfacial silicon dioxide layer initially hinders the out-diffusion of said phosphorus atoms into said overlying arsenic insitu doped polysilicon layer to provide sufficient time for the phosphorus atoms to breakup said first interfacial silicon dioxide layer during which the phosphorus atoms also break up said second interfacial silicon dioxide layer prior to out-diffusing into said arsenic insitu doped polysilicon layer.
Claim 22
Dependent Claim
39 words
The method as recited in claim 14, wherein said phosphorus insitu doped polysilicon layer has a thickness in the range of 100-500 Å and said arsenic insitu doped polysilicon layer has a thickness in the range of 500-5000 Å.
Claim 23
Dependent Claim
21 words
The method as recited in claim 14, wherein said annealing step is performed at a temperature range of approximately 900°-1100° C.
Claim 24
Dependent Claim
14 words
The method as recited in claim 14, wherein said semiconductor device comprises memory devices.
Claim 25
Dependent Claim
39 words
The method as recited in claim 14, wherein said annealing step is performed such that the arsenic atoms and the phosphorus atoms diffuse into the conductive area no more than 500-1000 Å from the edge of said contact formation.
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