US5541131A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Peeling free metal silicide films using ion implantation
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1991-02-01
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Granted: 1996-07-30
•
Expires: 2011-02-01
Abstract
Abstract A method is described for fabricating a lightly doped drain MOSFET integrated circuit device which overcomes the polycide peeling problems. A pattern of gate electrode structures is formed upon a semiconductor substrate which each includes a gate oxide, a polysilicon layer and an amorphous refractory metal silicide. The resulting structure may be annealed in oxygen at this time to change the refractory metal silicide from it deposited amorphous phase into its crystalline phase. This causes the formation of a thin layer of silicon dioxide upon the exposed silicon substrate, the exposed polysilicon layer and the exposed metal silicide layer. A pattern of lightly doped regions in the substrate is formed by ion implantation using the polycide gate structures as the mask. A dielectric layer is blanket deposited over the surfaces and spacer structures formed by anisotropic etching. A pattern of heavily doped regions in the substrate is formed by ion implantation using the polycide structures with spacer structures as the mask to produce the lightly doped drain source/drain structures of an MOSFET device. The silicon oxide layer on the top surface of the metal silicate layer was removed by etching. Silicon ions are now implanted into the metal silicide layer to supply an excess of silicon ions at the surface of the metal silicide layer. The integrated circuit device is completed by forming a passivation layer over the structures described and appropriate electrical connecting structures thereover.
Inventors
- 👤 Chue-San Yoo
- 👤 Ting-Hwang Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:19
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; Y; Y10; Y10S; Y10S148/00; Y10S148/147
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
247 words
The method for fabricating a lightly doped drain MOS FET integrated circuit device comprising: forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide, a polysilicon layer, a refractory metal silicide layer and a silicon oxide layer over top and sidewall portions of the said gate oxide, said polysilicon layer and said refractory metal silicide layer; forming lightly doped regions in said substrate by ion implantation using said gate electrode structures as a mask; blanket depositing a low temperature silicon dioxide layer over the surfaces of the gate electrode structures; etching the said low temperature silicon dioxide layer to form dielectric spacer structures upon the sidewalls of each of said gate electrode structures and over the adjacent portions of said substrate, and to remove the said silicon oxide layer from the top surfaces of said refractory metal silicide layer; forming heavily doped regions in said substrate by ion implantation using the said gate electrode structures with said dielectric spacer structures as a mask to produce said lightly doped drain under said dielectric spacer structures of an MOS FET device; ion implanting silicon ions into the top surface of said refractory metal silicide layer to provide extra silicon atoms at the surface of said refractory metal silicide layer; and forming a passivation layer over the said structures and appropriate electrical connecting structures thereover to electrically connect the said gate electrode structures and source/drain elements to form said integrated circuit device.
Claim 2
Independent Claim
247 words
The method for fabricating a lightly doped drain MOS FET integrated circuit device comprising: forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide, a polysilicon layer, a refractory metal silicide layer and a silicon oxide layer over top and sidewall portions of the said gate oxide, said polysilicon layer and said refractory metal silicide layer; forming lightly doped regions in said substrate by ion implantation using said gate electrode structures as a mask; blanket depositing a low temperature silicon dioxide layer over the surfaces of the gate electrode structures; etching the said low temperature silicon dioxide layer to form dielectric spacer structures upon the sidewalls of each of said gate electrode structures and over the adjacent portions of said substrate, and to remove the said silicon oxide layer from the top surfaces of said refractory metal silicide layer; forming heavily doped regions in said substrate by ion implantation using the said gate electrode structures with said dielectric spacer structures as a mask to produce said lightly doped drain under said dielectric spacer structures of an MOS FET device; ion implanting silicon ions into the top surface of said refractory metal silicide layer to provide extra silicon atoms at the surface of said refractory metal silicide layer; and forming a passivation layer over the said structures and appropriate electrical connecting structures thereover to electrically connect the said gate electrode structures and source/drain elements to form said integrated circuit device.
Claim 3
Dependent Claim
47 words
The method off claim 1 wherein the said ion implanting of silicon is at a dosage of between about 5 E 14 to 1 E 15 atoms per square cm. and is annealed at a temperature of between about 850° to 920° C. in an inert atmosphere.
Claim 4
Dependent Claim
47 words
The method of claim 1 wherein the said ion implanting of silicon is at a dosage of between about 5 E 14 to 1 E 15 atoms per square cm. and is annealed at a temperature of between about 850° to 920° C. in an oxidizing atmosphere.
Claim 5
Dependent Claim
19 words
The method of claim 1 wherein the said refractory metal silicide is deposited in situ by chemical vapor deposition.
Claim 6
Dependent Claim
14 words
The method of claim 4 wherein the said refractory metal silicide is tungsten disilicide.
Claim 7
Dependent Claim
35 words
The method of claim 5 wherein the thickness of said tungsten disilicide layer is between about 2250 and 2750 Angstroms and the thickness of the said polysilicon layer is between about 2250 and 2750 Angstroms.
Claim 8
Dependent Claim
43 words
The method of claim 1 wherein the thickness of the said refractory metal silicide layer is between about 2250 to 2750 Angstroms, the said polysilicon layer is heavily doped and the thickness of said polysilicon layer is between about 2250 to 2750 Angstroms.
Claim 9
Dependent Claim
31 words
The method of claim 1 wherein the said lightly doped regions are N- doped and said heavily doped regions are N+ doped to form an N channel MOS FET integrated circuit.
Claim 10
Dependent Claim
34 words
The method of claim 1 wherein both P and N lightly doped drain MOS FET integrated circuit devices are formed on said substrate to provide CMOS FET circuit capability within said integrated circuit device.
Claim 11
Dependent Claim
43 words
The method of claim 1 wherein the thickness of said low temperature silicon dioxide layer is between about 2250 to 2750 Angstroms, and the said low temperature silicon dioxide layer is formed by low temperature chemical vapor deposition at less than 700° C.
Claim 12
Dependent Claim
37 words
The method of claim 1 wherein the said dielectric spacer structures are formed with a low temperature TEOS chemical vapor deposition method and a reactive ion anisotropic etching process is used to produce said dielectric spacer structures.
Claim 13
Dependent Claim
72 words
The method of claim 1 wherein after the formation of the gate oxide, the polysilicon layer, and the refractory metal silicide layer, the silicon oxide layer is formed on the top and sidewall portions of the gate oxide, the polysilicon layer and the refractory metal silicide layer by annealing in an oxygen atmosphere, during said annealing the said refractory metal silicide layer is transformed from its amorphous phase to its crystalline phase.
Claim 14
Independent Claim
240 words
The method for fabricating a lightly doped drain MOS FET integrated circuit device comprising: forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide, a polysilicon layer, a tungsten disilicide layer and a silicon oxide layer, said silicon oxide layer formed over the surfaces of said gate oxide, said polysilicon layer, and said tungsten disilicide layer by annealing; forming lightly doped regions in said substrate by ion implantation using said gate electrode structures as a mask; blanket depositing a low temperature silicon dioxide layer over the surfaces of the gate electrode structures; etching the said low temperature silicon dioxide layer to form dielectric spacer structures upon the sidewalls of each of said gate electrode structures and over the adjacent portions of said substrate, and removing said silicon oxide layer from the top surface of said tungsten disilicide layer; forming heavily doped regions in said substrate by ion implantation using the said gate electrode structures with said dielectric spacer structures as a mask to produce said lightly doped drain under said dielectric spacer structures of an MOS FET device; ion implanting silicon ions into the said tungsten disilicide layer to provide extra silicon at the surface of said tungsten disilicide layer; and forming a passivation layer over the said structures and appropriate electrical connecting structures therover to electrically connect the said gate electrode structures and source/drain elements to form said integrated circuit device.
Claim 15
Independent Claim
240 words
The method for fabricating a lightly doped drain MOS FET integrated circuit device comprising: forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide, a polysilicon layer, a tungsten disilicide layer and a silicon oxide layer, said silicon oxide layer formed over the surfaces of said gate oxide, said polysilicon layer, and said tungsten disilicide layer by annealing; forming lightly doped regions in said substrate by ion implantation using said gate electrode structures as a mask; blanket depositing a low temperature silicon dioxide layer over the surfaces of the gate electrode structures; etching the said low temperature silicon dioxide layer to form dielectric spacer structures upon the sidewalls of each of said gate electrode structures and over the adjacent portions of said substrate, and removing said silicon oxide layer from the top surface of said tungsten disilicide layer; forming heavily doped regions in said substrate by ion implantation using the said gate electrode structures with said dielectric spacer structures as a mask to produce said lightly doped drain under said dielectric spacer structures of an MOS FET device; ion implanting silicon ions into the said tungsten disilicide layer to provide extra silicon at the surface of said tungsten disilicide layer; and forming a passivation layer over the said structures and appropriate electrical connecting structures therover to electrically connect the said gate electrode structures and source/drain elements to form said integrated circuit device.
Claim 16
Dependent Claim
40 words
The method of claim 13 wherein the said tungsten disilicide layer has a thickness of between about 2250 to 2750 Angstroms and the said annealing is done at a temperature of less than 920° C. for less than 30 minutes.
Claim 17
Dependent Claim
37 words
The method of claim 13 wherein the said dielectric spacer structures are formed with a low temperature TEOS chemical vapor deposition method and a reactive ion anisotropic etching process is used to produce said dielectric spacer structures.
Claim 18
Dependent Claim
126 words
Method for contacting in an integrated circuit manufacturing process a metal silicide conductive line through a passivation glasseous layer comprising: etching an opening to said metal silicide conductive line through the said glasseous layer; ion implanting ions from the group consisting of silicon and arsenic with a dosage of greater than about 5 E 14 to 1 E 15 and 8 E 15 to 1 E 16 atoms/square cm., respectively, into the said exposed metal silicide conductive line; heating the structure to a temperature to cause the said glasseous layer to flow and to round off the sharp corners at the surface of the said opening; and forming a conductive contact through the said opening in the said glasseous layer to said metal silicide conductive line.
Claim 19
Dependent Claim
126 words
Method for contacting in an integrated circuit manufacturing process a metal silicide conductive line through a passivation glasseous layer comprising: etching an opening to said metal silicide conductive line through the said glasseous layer; ion implanting ions from the group consisting of silicon and arsenic with a dosage of greater than about 5 E 14 to 1 E 15 and 8 E 15 to 1 E 16 atoms/square cm., respectively, into the said exposed metal silicide conductive line; heating the structure to a temperature to cause the said glasseous layer to flow and to round off the sharp corners at the surface of the said opening; and forming a conductive contact through the said opening in the said glasseous layer to said metal silicide conductive line.
Claim 20
Dependent Claim
31 words
The method of claim 16 wherein the said glasseous layer is borophosphosilicate glass and the heating is to a temperature of between about 850° to 920° C. in a nitrogen atomosphere.
Claim 21
Dependent Claim
21 words
The method of claim 17 wherein the metal silicide conductive line is tungsten disilicide and the said conductive contact is aluminium.
Claim 22
Dependent Claim
36 words
The method of claim 16 wherein said glasseous layer is a composite of silicon dioxide and borophosphosilicate glass and the heating is to a temperature of between about 850° to 920° C. in an inert atmosphere.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-30 | 2000-01-29 | 2000-07-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-30 | 2004-01-29 | 2004-07-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-30 | 2008-01-29 | 2008-07-30 | $7700.00 | Window Closed / Lapsed |