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US5541122A
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Method of fabricating an insulated-gate bipolar transistor
Assignee: NXP USA Inc
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Filing: 1995-04-03
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Granted: 1996-07-30
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Expires: 2015-04-03
Abstract
Abstract A method of fabricating a fast-switching, low-R(on) insulated-gate bipolar transistor including providing an N-type semiconductor wafer with a planar surface, forming a thin heavily-doped layer, having a concentration in the range of 3×10 17 /cm 3 to 1×10 19 /cm 3 , in the wafer adjacent the planar surface, providing a P-type semiconductor wafer, and bonding a surface of the P-type wafer to the planar surface of the N-type wafer. An emitter and a gate are then formed in the N-type wafer in the usual manner and a collector is formed on the P-type wafer.
Inventors
- 👤 Shang-hui L. Tu
- 👤 Gordon Tam
- 👤 Pak Tam
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 13:31
CPC Classifications
H; H10; H10D; H10D12/00; H10D12/01; H10D12/031; H10D12/032; H10D12/411; H10D12/441; Y; Y10; Y10S; Y10S148/00; Y10S148/126
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
130 words
A method of fabricating an insulated-gate bipolar transistor comprising the steps of: providing a substrate having a first conductivity type with a planar surface; forming a heavily-doped layer of the first conductivity type, having a concentration in a range of 3×10 17 /cm 3 to 1×10 19 /cm 3 , in the substrate adjacent the planar surface; providing a layer of semiconductor material with a second conductivity type having first and second opposed surfaces; bonding the first surface of the layer of semiconductor material to the planar surface of the substrate, so that the heavily doped layer of the first conductivity type is adjacent the layer of the semiconductor material having a second conductivity type; and forming an emitter and a gate on the second surface of the semiconductor layer.
Claim 2
Independent Claim
130 words
A method of fabricating an insulated-gate bipolar transistor comprising the steps of: providing a substrate having a first conductivity type with a planar surface; forming a heavily-doped layer of the first conductivity type, having a concentration in a range of 3×10 17 /cm 3 to 1×10 19 /cm 3 , in the substrate adjacent the planar surface; providing a layer of semiconductor material with a second conductivity type having first and second opposed surfaces; bonding the first surface of the layer of semiconductor material to the planar surface of the substrate, so that the heavily doped layer of the first conductivity type is adjacent the layer of the semiconductor material having a second conductivity type; and forming an emitter and a gate on the second surface of the semiconductor layer.
Claim 3
Dependent Claim
30 words
A method of fabricating an insulated-gate bipolar transistor as claimed in claim 1 wherein the step of forming a heavily-doped layer includes implanting impurities and annealing to activate the impurities.
Claim 4
Dependent Claim
22 words
A method of fabricating an insulated-gate bipolar transistor as claimed in claim 2 wherein the step of implanting impurities includes implanting phosphorous.
Claim 5
Dependent Claim
33 words
A method of fabricating an insulated-gate bipolar transistor as claimed in claim 3 wherein the step of implanting phosphorous includes implanting a dose of approximately 5×10 14 and 1×10 16 /cm 2 phosphorous.
Claim 6
Dependent Claim
42 words
A method of fabricating an insulated-gate bipolar transistor as claimed in claim 2 including in addition a step of implanting impurities of the second conductivity type in the layer of semiconductor material adjacent the first surface and annealing to activate the impurities.
Claim 7
Dependent Claim
27 words
A method of fabricating an insulated-gate bipolar transistor as claimed in claim 5 wherein the step of annealing is performed at a temperature of approximately 1080° C.
Claim 8
Dependent Claim
28 words
A method of fabricating an insulated-gate bipolar transistor as claimed in claim 5 wherein the step of implanting impurities in the layer of semiconductor material includes implanting boron.
Claim 9
Dependent Claim
46 words
A method of fabricating an insulated-gate bipolar transistor as claimed in claim 7 wherein the step of implanting boron includes implanting a dose of approximately 1×10 15 to 1×10 16 /cm 2 boron wherein an electrical junction is formed in a portion of the semiconductor material.
Claim 10
Dependent Claim
67 words
A method of fabricating an insulated-gate bipolar transistor as claimed in claim 5 including in addition a step of removing any additional material formed on the planar surface of the substrate and the first surface of the layer of semiconductor material by the annealing step prior to the step of bonding the first surface of the layer of semiconductor material to the planar surface of the substrate.
Claim 11
Dependent Claim
48 words
A method of fabricating an insulated-gate bipolar transistor as claimed in claim 9 wherein the step of bonding the first surface of the layer of semiconductor material to the planar surface of the substrate includes wafer bonding at a temperature of approximately 900°-1100° C. for approximately 30-90 minutes.
Claim 12
Dependent Claim
31 words
A method of fabricating an insulated-gate bipolar transistor as claimed in claim 9 wherein the step of forming the heavily-doped layer includes forming the layer less than approximately 10 microns thick.
Claim 13
Independent Claim
144 words
A method of fabricating an insulated-gate bipolar transistor comprising the steps of: providing a first semiconductor wafer having a first conductivity type with a planar surface and a second opposed surface; forming a first heavily-doped layer of the first conductivity type in the first semiconductor wafer adjacent the planar surface; providing a second semiconductor wafer having a second conductivity type with a planar surface and a second opposed surface; forming a second heavily-doped layer in the second semiconductor wafer adjacent the planar surface; bonding the planar surface of the first semiconductor wafer to the planar surface of the second semiconductor wafer to form a buffer region including the first and second heavily doped layers; and forming an emitter and a gate on the second opposed surface of the first semiconductor wafer and a collector on the second opposed surface of the second semiconductor wafer.
Claim 14
Independent Claim
144 words
A method of fabricating an insulated-gate bipolar transistor comprising the steps of: providing a first semiconductor wafer having a first conductivity type with a planar surface and a second opposed surface; forming a first heavily-doped layer of the first conductivity type in the first semiconductor wafer adjacent the planar surface; providing a second semiconductor wafer having a second conductivity type with a planar surface and a second opposed surface; forming a second heavily-doped layer in the second semiconductor wafer adjacent the planar surface; bonding the planar surface of the first semiconductor wafer to the planar surface of the second semiconductor wafer to form a buffer region including the first and second heavily doped layers; and forming an emitter and a gate on the second opposed surface of the first semiconductor wafer and a collector on the second opposed surface of the second semiconductor wafer.
Claim 15
Dependent Claim
42 words
A method of fabricating an insulated-gate bipolar transistor as claimed in claim 12 wherein the step of forming a first heavily-doped layer in the first semiconductor wafer includes implanting a dose of approximately 5×10 14 to 1×10 16 /cm 2 of phosphorous.
Claim 16
Dependent Claim
42 words
A method of fabricating an insulated-gate bipolar transistor as claimed in claim 13 wherein the step of forming a second heavily-doped layer in the second semiconductor wafer includes implanting a dose of approximately 1×10 15 to 1×10 16 /cm 2 of boron.
Claim 17
Dependent Claim
50 words
A method of fabricating an insulated-gate bipolar transistor as claimed in claim 14 wherein the step of bonding the wafers to form the buffer region includes etching the planar surfaces of both the first and second semiconductor wafers to remove any material formed on the surface during the implanting step.
Claim 18
Dependent Claim
50 words
A method of fabricating an insulated-gate bipolar transistor as claimed in claim 15 wherein the step of etching the planar surfaces of both the first and second semiconductor wafers includes etching sufficiently to form a layer of semiconductor material during the bonding step of less than approximately 10 microns thick.
Claim 19
Dependent Claim
53 words
A method of fabricating an insulated-gate bipolar transistor as claimed in claim 16 including in addition a step of lapping the planar surface of the first semiconductor wafer, subsequent to the bonding step and before the step of forming an emitter and a gate, to form a bonded wafer having a specific thickness.
References Cited (Backward Citations)
US5141887A
Cited
US5141889A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-30 | 2000-01-29 | 2000-07-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-30 | 2004-01-29 | 2004-07-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-30 | 2008-01-29 | 2008-07-30 | $7700.00 | Window Closed / Lapsed |