US5141889A
Expired / Lapsed
US
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Method of making enhanced insulated gate bipolar transistor
Assignee: Semiconductor Components Industries LLC
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Filing: 1991-06-17
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Granted: 1992-08-25
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Expires: 2011-06-17
Abstract
Abstract An insulated gate bipolar device is formed on a multiple conductivity substrate. The multiple conductivity substrate comprises interspersed regions of N+ and P+ semiconductor material. In a preferred embodiment, the N+ and P+ regions are arranged in a checkerboard, mosaic pattern on a bottom side of the substrate. The P+ region serves to conductivity modulate an N epitaxial layer in which the IGBT structure is formed while the N+ regions improve low current conductivity, reduce minority carrier recombination time, and make an integral drain source diode accessible from the drain and source electrodes.
Inventors
- 👤 Lewis E. Terry
- 👤 Stephen P. Robb
- 👤 Robert E. Rutter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:02
CPC Classifications
H; H10; H10D; H10D12/00; H10D12/01; H10D12/031; H10D12/032; H10D62/00; H10D62/10; H10D62/13; H10D62/141; H10D62/142; Y; Y10; Y10S; Y10S148/00; Y10S148/126
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
160 words
A method for manufacturing an enhanced insulated gate bipolar transistor (EIGBT) comprising: providing a first <100> semiconductor substrate of a first conductivity type having a top and a bottom surface; forming a plurality of first conductivity type regions in the first substrate; forming a plurality of second conductivity type regions in the first substrate, wherein the first and second conductivity type regions are arranged in a checkerboard mosaic pattern; forming a single crystal semiconductor layer having a bottom surface laminated to the top surface of the first substrate and a top surface which is exposed; forming a filed effect transistor having gate and source electrodes in the exposed top surface; polishing the bottom side of the first substrate to expose the plurality of first and second conductivity type regions; and forming a drain electrode on the bottom surface of the first substrate coupled to both the plurality of first conductivity type regions and the plurality of second conductivity type regions.
Claim 2
Independent Claim
160 words
A method for manufacturing an enhanced insulated gate bipolar transistor (EIGBT) comprising: providing a first <100> semiconductor substrate of a first conductivity type having a top and a bottom surface; forming a plurality of first conductivity type regions in the first substrate; forming a plurality of second conductivity type regions in the first substrate, wherein the first and second conductivity type regions are arranged in a checkerboard mosaic pattern; forming a single crystal semiconductor layer having a bottom surface laminated to the top surface of the first substrate and a top surface which is exposed; forming a filed effect transistor having gate and source electrodes in the exposed top surface; polishing the bottom side of the first substrate to expose the plurality of first and second conductivity type regions; and forming a drain electrode on the bottom surface of the first substrate coupled to both the plurality of first conductivity type regions and the plurality of second conductivity type regions.
Claim 3
Dependent Claim
96 words
The method of claim 1 wherein the step of forming a plurality of second conductivity type regions further comprises the steps of: providing an etch resistant mask layer on the top side of the first substrate; forming the checkerboard mosaic pattern in the mask layer; etching the top side of the first substrate through the mask layer to form a plurality of holes of a predetermined depth; refilling the holes by epitaxially depositing semiconductor material of a second conductivity type; and polishing the top side of the first substrate to expose the epitaxially depositing semiconductor material.
Claim 4
Dependent Claim
55 words
The method of claim 1 wherein the step of forming a plurality of first and second conductivity type regions further comprises the steps of: pre-depositing N-type and P-type dopant atoms on the top surface of the first substrate in the checkerboard mosaic pattern; and simultaneously diffusing both types of dopant atoms to a predetermined depth.
Claim 5
Dependent Claim
41 words
The method of claim 1 wherein the step of forming a single crystal semiconductor layer having a bottom surface laminated to the top surface of the first substrate and a top surface which is exposed comprises epitaxially depositing the semiconductor layer.
Claim 6
Dependent Claim
50 words
The method of claim 1 wherein the step of forming a single crystal semiconductor layer having a bottom surface laminated to the top surface of the first substrate and a top surface which is exposed comprises bonding a second semiconductor substrate to the top surface of the first semiconductor substrate.
Claim 7
Dependent Claim
18 words
The method of claim 2 or 3 wherein the predetermined depth is approximately fifty to seventy five microns.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-25 | 1996-02-24 | 1996-08-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-25 | 2000-02-24 | 2000-08-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-25 | 2004-02-24 | 2004-08-25 | $7700.00 | Window Closed / Lapsed |