Method and apparatus for sequential programming of the bits in a word of a flash EEPROM memory array

Claim 2

A computer system comprising: a central processor; a memory arrangement comprising: a flash EEPROM memory array including a plurality of floating gate field effect transistor devices, each floating gate field effect transistor device storing at least one bit, a first charge pump for providing a first positive voltage to be applied to drain terminals of the floating gate field effect transistor devices during a programming operation, a plurality of switching circuits each coupled to receive the first positive voltage provided by the first charge pump and for transferring that first positive voltage to selected subgroups of a plurality of subgroups of bitlines of the array, and logic circuitry coupled to the plurality of switching circuits for enabling the plurality of switching circuits in a selected order, such that a switching circuit of the plurality of switching circuits is enabled to couple the first positive voltage to a selected subgroup of the plurality of subgroups of bitlines until the floating gate field effect transistor devices coupled to the bitlines to be programmed are programmed; and a system bus for transferring data and addresses between the central processor and the memory arrangement.

Claim 3

A computer system as claimed in claim 1, wherein the logic circuitry comprises a state machine, said state machine enabling each of the plurality of switching circuits in a selected sequential order such that the first voltage is applied individually to each subgroup until selected bits of each subgroup have been programmed.

Claim 4

The computer system as set forth in claim 2, further comprising column decode circuitry coupled to the switching circuit to select the bitlines of a subgroup to connect to receive the first voltage such that selected bits are programmed.

Claim 5

A computer system as claimed in claim 1 in which each of the subgroups includes four bitlines.

Claim 6

A computer system as claimed in claim 1 in which the plurality of switching circuits comprises four switching circuits, a switching circuit of the plurality of switching circuits coupled to a corresponding subgroup of four bitlines.

Claim 7

A computer system as claimed in claim 1 in which the plurality of means for transferring the first positive voltage to a selected plurality of subgroups of bitlines of the array means comprises four switching circuits, a switching circuit of the plurality of switching circuits coupled to a corresponding subgroup of four bitlines.

Claim 8

A memory arrangement comprising: a flash EEPROM memory array including a plurality of floating gate field effect transistor devices, each floating gate field effect transistor device storing at least one bit, a first charge pump for providing a first positive voltage to be applied to drain terminals of the floating gate field effect transistor devices during a programming operation, a plurality of switching circuits each coupled to receive the first positive voltage provided by the first charge pump and for transferring that first positive voltage to a selected subgroups of a plurality of subgroups of bitlines of the array, and logic circuitry coupled to the plurality of switching circuits for enabling the plurality of switching circuits in a selected order such that a switching circuit of the plurality of switching circuits is enabled to couple the first positive voltage to a selected subgroup of the plurality of subgroups of bitlines until the floating gate field effect transistor devices coupled to the bitlines to be programmed are programmed.

Claim 9

A memory arrangement comprising: a flash EEPROM memory array including a plurality of floating gate field effect transistor devices, each floating gate field effect transistor device storing at least one bit, a first charge pump for providing a first positive voltage to be applied to drain terminals of the floating gate field effect transistor devices during a programming operation, a plurality of switching circuits each coupled to receive the first positive voltage provided by the first charge pump and for transferring that first positive voltage to a selected subgroups of a plurality of subgroups of bitlines of the array, and logic circuitry coupled to the plurality of switching circuits for enabling the plurality of switching circuits in a selected order such that a switching circuit of the plurality of switching circuits is enabled to couple the first positive voltage to a selected subgroup of the plurality of subgroups of bitlines until the floating gate field effect transistor devices coupled to the bitlines to be programmed are programmed.

Claim 10

A memory arrangement as claimed in claim 7, wherein the logic circuitry comprises a state machine, said state machine enabling each of the plurality of switching circuits in a selected sequential order such that the first voltage is applied individually to each subgroup until selected bits of each subgroup have been programmed.

Claim 11

The computer system as set forth in claim 8, further comprising column decode circuitry coupled to the switching circuit to select the bitlines of a subgroup to connect to receive the first voltage such that selected bits are programmed.

Claim 12

A memory arrangement as claimed in claim 7 in which each of the subgroups includes four bitlines.

Claim 13

A memory arrangement as claimed in claim 7 in which the plurality of switching circuits comprises four switching circuits, a switching circuit of the plurality of switching circuits coupled to a corresponding subgroup of four bitlines.

Claim 14

A computer system comprising: central processing means; means for providing storage of data comprising flash EEPROM memory array means including a plurality of floating gate field effect transistor devices, each floating gate field effect transistor device storing at least one bit, charge pump means for providing a first positive voltage to be applied to drain terminals of the floating gate field effect transistor devices during a programming operation, a plurality of means for transferring the first positive voltage to selected subgroups of a plurality of subgroups of bitlines of the array means, and means for enabling in a selected order the plurality of means for transferring the first positive voltage to a selected subgroup of a plurality of subgroups of bitlines of the array means, such that a selected means for transferring of the plurality of means for transferring is enabled to couple the first positive voltage to a selected subgroup of the selected plurality of subgroups of bitlines until selected floating gate field effect transistor devices coupled to the bitlines are programmed; and system bus means for transferring data and addresses between the central processing means and the means for providing storage for data.

Claim 15

A computer system comprising: central processing means; means for providing storage of data comprising flash EEPROM memory array means including a plurality of floating gate field effect transistor devices, each floating gate field effect transistor device storing at least one bit, charge pump means for providing a first positive voltage to be applied to drain terminals of the floating gate field effect transistor devices during a programming operation, a plurality of means for transferring the first positive voltage to selected subgroups of a plurality of subgroups of bitlines of the array means, and means for enabling in a selected order the plurality of means for transferring the first positive voltage to a selected subgroup of a plurality of subgroups of bitlines of the array means, such that a selected means for transferring of the plurality of means for transferring is enabled to couple the first positive voltage to a selected subgroup of the selected plurality of subgroups of bitlines until selected floating gate field effect transistor devices coupled to the bitlines are programmed; and system bus means for transferring data and addresses between the central processing means and the means for providing storage for data.

Claim 16

A computer system as claimed in claim 12, wherein the means for enabling in a selected sequential order the plurality of means for transferring the first positive voltage to a selected plurality of subgroups of bitlines of the array means is a state machine, said state machine enabling each of the plurality of means for transferring the first positive voltage to a selected plurality of subgroups of bitlines of the array means such that the first voltage is applied individually to each subgroup until selected bits of each subgroup have been programmed.

Claim 17

A computer system as claimed in claim 12 in which each of the subgroups includes four bitlines.

Claim 18

An arrangement for providing storage of data comprising: flash EEPROM memory array means including a plurality of floating gate field effect transistor devices, each floating gate field effect transistor device storing at least one bit, charge pump means for providing a first positive voltage to be applied to drain terminals of the floating gate field effect transistor devices during a programming operation, a plurality of means for transferring the first positive voltage to selected subgroups of a plurality of subgroups of bitlines of the array means, and means for enabling in a selected order the plurality of means for transferring the first positive voltage to a selected selected subgroup of a plurality of subgroups of bitlines of the array means, such that a selected means for transferring of the plurality of means for transferring is enabled to couple the first positive voltage to a selected subgroup of the selected plurality of subgroups of bitlines until selected floating gate field effect tranistor devices coupled to the bitlines are programmed.

Claim 19

An arrangement for providing storage of data comprising: flash EEPROM memory array means including a plurality of floating gate field effect transistor devices, each floating gate field effect transistor device storing at least one bit, charge pump means for providing a first positive voltage to be applied to drain terminals of the floating gate field effect transistor devices during a programming operation, a plurality of means for transferring the first positive voltage to selected subgroups of a plurality of subgroups of bitlines of the array means, and means for enabling in a selected order the plurality of means for transferring the first positive voltage to a selected selected subgroup of a plurality of subgroups of bitlines of the array means, such that a selected means for transferring of the plurality of means for transferring is enabled to couple the first positive voltage to a selected subgroup of the selected plurality of subgroups of bitlines until selected floating gate field effect tranistor devices coupled to the bitlines are programmed.

Claim 20

An arrangement for providing storage of data as claimed in claim 15, wherein the means for enabling in a selected sequential order the plurality of means for transferring the first positive voltage to a selected plurality of subgroups of bitlines of the array means is a state machine, said state machine enabling each of the plurality of means for transferring the first positive voltage to a selected plurality of subgroups of bitlines of the array means such that the first voltage is applied individually to each subgroup until selected bits of each subgroup have been programmed.

Claim 21

An arrangement for providing storage of data as claimed in claim 15 in which each of the subgroups includes four bitlines.

Claim 22

An arrangement for providing storage of data as claimed in claim 15 in which the plurality of means for transferring the first positive voltage to a selected plurality of subgroups of bitlines of the array means comprises four switching circuits, a switching circuit of the plurality of switching circuits coupled to a corresponding subgroup of four bitlines.

Claim 25

A method as claimed in claim 19 which includes the further step of testing after each step of applying a enabling pulse to determine whether additional subgroups of bits exist in the word which have not yet been programmed.

Claim 26

A method as claimed in claim 19 which includes the further step of verifying that all bits of a selected word have been programmed.