Analog-to-digital converter

Claim 2

An analog to digital converter comprising: at least one first analog memory means (x) having an input port for receiving reference signal packets (u) and a partial output drive port for outputting the i-th output signal packet (Q out (i)) defined by: Q.sub.out (i)=U·(1-a).sup.i-1 ·a where a is a value satisfying 1>a>0, and i=1, 2, 3 . . . ; at least two second analog memory means (Y) having a function to accumulate input signal packets applied thereto, said at least two second analog memory means (Y) being connected to said at least one first analog memory means (x) so as to receive the i-th output signal packets outputted thereby; at least two signal packet measuring means for measuring the size of the signal packets stored in said two second analog memory means (Y); at least one signal comparator means for comparing outputs of said two signal packet measuring means and generating digital output bits (d(i)); and a signal packet routing mechanism for selectively routing output signal packets from said first analog memory means (x) to one of said second analog memory means (Y) according to an output digital signal from said at least one signal comparator means.

Claim 3

An analog to digital converter comprising: at least one first analog memory means (x) having an input port for receiving reference signal packets (u) and a partial output drive port for outputting the i-th output signal packet (Q out (i)) defined by: Q.sub.out (i)=U·(1-a).sup.i-1 ·a where a is a value satisfying 1>a>0, and i=1, 2, 3 . . . ; at least one recursive shift register including at least two second analog memory means (Y) wherein signal packets are allowed to be transferred in re-circulating manner, constructing virtual memory media that rotate virtually on said recursive shift register, said at least one of said at least two second analog memory means (Y) being connected to said at least one first analog memory means (x) so as to receive the i-th output signal packets outputted thereby; at least one signal packet measuring means for measuring the size of the signal packets stored in said at least one of said at least two second analog memory means (Y); at least one signal comparator means for comparing outputs of said at least one signal packet measuring means and generating digital output bits (d(i)); at least one sample and hold circuit for holding an analog signal level measured by said at least one signal packet measuring means and for supplying an input to said at least one comparator means; and a shift timing controller for controlling the shift timing of a plurality of shift registers including said recursive shift register, in accordance with the output digital bit determined by said at least one comparator means, in order to execute an addition of the signal packets by partially shifting said recursive shift register or in order to execute an addition transferring output signal packets of said first analog memory means (X) to one of a plurality of memory slots at a selected timing, said memory slots being each formed of said virtual memory media.

Claim 4

An analog to digital converter comprising: at least one first analog memory means (x) having an input port for receiving reference signal packets (u) and a partial output drive port for outputting the i-th output signal packet (Q out (i)) defined by: Q.sub.out (i)=U·(1-a).sup.i-1 ·a where a is a value satisfying 1>a>0, and i=1, 2, 3 . . . ; at least one recursive shift register including at least two second analog memory means (Y) wherein signal packets are allowed to be transferred in re-circulating manner, constructing virtual memory media that rotate virtually on said recursive shift register, said at least one of said at least two second analog memory means (Y) being connected to said at least one first analog memory means (x) so as to receive the i-th output signal packets outputted thereby; at least one signal packet measuring means for measuring the size of the signal packets stored in said at least one of said at least two second analog memory means (Y); at least one signal comparator means for comparing outputs of said at least one signal packet measuring means and generating digital output bits (d(i)); at least one sample and hold circuit for holding an analog signal level measured by said at least one signal packet measuring means and for supplying an input to said at least one comparator means; and a shift timing controller for controlling the shift timing of a plurality of shift registers including said recursive shift register, in accordance with the output digital bit determined by said at least one comparator means, in order to execute an addition of the signal packets by partially shifting said recursive shift register or in order to execute an addition transferring output signal packets of said first analog memory means (X) to one of a plurality of memory slots at a selected timing, said memory slots being each formed of said virtual memory media.

Claim 5

An analog to digital converter according to claim 2, wherein at least one input signal packet has been inputted to said memory slots at the starting timing of conversion; and the output signal packets of said first analog memory means (X) is selectively added to one of said memory slots including the memory slots which initially store input signal packets, directly or indirectly.

Claim 6

An analog to digital converter according to claim 2, wherein at least one input signal packet is measured by said signal packet measuring means and stored in said sample and hold circuit prior to the starting timing of conversion to provide an input signal level to said comparator means; and the output signal packets of said first analog memory means are selectively added to one of said memory slots which does not hold input signal packets stored therein.

Claim 7

An analog to digital converter according to claim 4, wherein the input signal packets are routed to the outside of said convertor after said input signal packet is measured by said signal packet measuring means.