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US5537060A
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Output buffer circuit for memory device
Assignee: MagnaChip Semiconductor Ltd
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Filing: 1994-12-22
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Granted: 1996-07-16
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Expires: 2014-12-22
Abstract
Abstract An output buffer circuit for a memory device comprising a pull-up path including first and second PMOS transistors for forming two parallel charging paths, and a pull-down path including first and second NMOS transistors for forming two parallel discharging paths. The first and second PMOS transistors are selectively operated according to a level of an output voltage at an output terminal to perform a charging operation for a load capacitance connected to the output terminal. The first and second NMOS transistors are selectively operated according to the level of the output voltage at the output terminal to perform a discharging operation for the load capacitance through a lead inductance.
Inventors
- 👤 Daebong Baek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 03:44
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057; H; H03; H03K; H03K17/00; H03K17/16; H03K17/161; H03K17/165; H03K17/166; H03K17/167
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
203 words
An output buffer circuit, comprising: an output terminal; and a pull-up path between a power supply voltage source and the output terminal, wherein said pull-up path includes: a first inverter for inverting an output enable signal, a first NOR gate for NORing a data signal and an output signal from said first inverter, a second NOR gate for NORing an output signal from said first inverter and an output voltage of said output terminal, first and second transmission gates being seiectively operated in response to an output signal from said second NOR gate to transfer an output signal from said first NOR gate to a first and a second switching means, respectively, means for preventing floating of said first and second transmission gates in a standby mode, a second inverter for inverting an output signal from said first transmission gate, a third inverter for inverting an output signal from said second transmission gate, and first and second switching means each connected between the power supply voltage source and the output terminal, being switched in response to output signals from said second and third inverters, respectively, to source current such that the first and second switching means form two respective parallel current sourcing paths.
Claim 2
Dependent Claim
203 words
An output buffer circuit, comprising: an output terminal; and a pull-up path between a power supply voltage source and the output terminal, wherein said pull-up path includes: a first inverter for inverting an output enable signal, a first NOR gate for NORing a data signal and an output signal from said first inverter, a second NOR gate for NORing an output signal from said first inverter and an output voltage of said output terminal, first and second transmission gates being seiectively operated in response to an output signal from said second NOR gate to transfer an output signal from said first NOR gate to a first and a second switching means, respectively, means for preventing floating of said first and second transmission gates in a standby mode, a second inverter for inverting an output signal from said first transmission gate, a third inverter for inverting an output signal from said second transmission gate, and first and second switching means each connected between the power supply voltage source and the output terminal, being switched in response to output signals from said second and third inverters, respectively, to source current such that the first and second switching means form two respective parallel current sourcing paths.
Claim 3
Dependent Claim
207 words
An output buffer circuit in accordance with claim 1, further comprising a pull-down path between the output terminal and ground, wherein said pull-down path includes: a first NAND gate for NANDing a data signal and an output signal from said first inverter, a second NAND gate for NANDing an output signal from said first inverter and an output voltage of said output terminal, third and fourth transmission gates being selectively operated in response to an output signal from said second NAND gate to transfer an output signal from said first NAND gate to a third and a fourth switching means, respectively, means for preventing floating of said first and second transmission gates in a standby mode, a fourth inverter for inverting an output signal from said third transmission gate, a fifth inverter for inverting an output signal from said fourth transmission gate, and third and fourth switching means each connected between the output terminal and ground, being switched in response to output signals from said fourth and fifth inverters, respectively, to sink current such that the third and fourth switching means form two respective parallel current sinking paths, said first and third switching means being complementarily connected and said second and fourth switching means being complementarily connected.
Claim 4
Dependent Claim
33 words
An output buffer circuit in accordance with claim 1, wherein said second NOR gate has a threshold voltage which can be adjusted to control a switching time of said parallel current sourcing paths.
Claim 5
Dependent Claim
33 words
An output buffer circuit in accordance with claim 2, wherein said second NAND gate has a threshold voltage which can be adjusted to control a switching time of said parallel current sinking paths.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-16 | 2000-01-15 | 2000-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-16 | 2004-01-15 | 2004-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-16 | 2008-01-15 | 2008-07-16 | $7700.00 | Window Closed / Lapsed |