← Back to Patent Explorer
US5536953A Expired / Lapsed US ⏱️ 0.0 years remaining

Wide bandgap semiconductor device including lightly doped active region

Assignee: Kobe Steel USA Inc
•
Filing: 1994-03-08
•
Granted: 1996-07-16
•
Expires: 2014-03-08
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A semiconductor device for providing stable operation over a relatively wide temperature range includes a wide bandgap semiconductor active region having an intentional dopant of a first conductivity type and an unintentional impurity of a second conductivity type which together produce a free carrier concentration at room temperature. The concentration of the intentional dopant in the active region is preferably less than 1×10 16 cm -3 and the concentration of the unintentional impurity is less than 0.1 times the intentional dopant concentration so that the intentional dopant concentration will be less than 1000 times the free carrier concentration at room temperature. The intentional dopant concentration supplies substantially all the majority free carriers in the active region. The wide bandgap semiconductor active region is preferably diamond, IV-IV carbides, III-V nitrides and phosphides and II-VI selenides, tellurides, oxides and sulfides. By lightly doping the active region to a level below 1×10 16 cm -3 , relatively uniform device characteristics can be achieved over a wide temperature range extending from room temperature to 1000 K and above.

Inventors

  • 👤 David L. Dreifus
  • 👤 Bradley A. Fox
  • 👤 Jesko A. von Windheim

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 20:32
CPC Classifications
H; H10; H10H; H10H20/00; H10H20/80; H10H20/81; H10H20/8215; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/674; H10D30/6741; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/328; H10D62/80; H10D62/83; H10D62/834; H10F; H10F30/00; H10F30/20; H10F30/21; H10F30/22; H10F30/221

Claims Analysis

Total Claims: 14
Claim 1
Independent Claim 184 words
A semiconductor device having enhanced thermal stability over a relatively wide temperature range and comprising: a diamond layer having a semiconducting active region therein and a drain region and a source region adjacent said semiconducting active region; an insulating layer adjacent said semiconducting active region; and gating means on said insulating layer for modulating said semiconducting active region so that the semiconductor device is an insulated-gate field effect transistor; said semiconducting active region including an intentional dopant of a first conductivity type and an unintentional impurity of a second conductivity type at respective concentrations to together produce at room temperature a compensated majority free carrier concentration of first conductivity type; and said intentional dopant concentration being relatively low at less than 1×10 16 cm -3 and supplying substantially all the majority free carriers in said active region when conduction in said active region is dominated by majority carrier transport and not by minority carrier transport, to thereby enhance thermal stability for the semiconductor device over a relatively wide temperature range, wherein the unintentional impurity concentration is less than 0.1 times the intentional dopant concentration.
Claim 2
Dependent Claim 184 words
A semiconductor device having enhanced thermal stability over a relatively wide temperature range and comprising: a diamond layer having a semiconducting active region therein and a drain region and a source region adjacent said semiconducting active region; an insulating layer adjacent said semiconducting active region; and gating means on said insulating layer for modulating said semiconducting active region so that the semiconductor device is an insulated-gate field effect transistor; said semiconducting active region including an intentional dopant of a first conductivity type and an unintentional impurity of a second conductivity type at respective concentrations to together produce at room temperature a compensated majority free carrier concentration of first conductivity type; and said intentional dopant concentration being relatively low at less than 1×10 16 cm -3 and supplying substantially all the majority free carriers in said active region when conduction in said active region is dominated by majority carrier transport and not by minority carrier transport, to thereby enhance thermal stability for the semiconductor device over a relatively wide temperature range, wherein the unintentional impurity concentration is less than 0.1 times the intentional dopant concentration.
Claim 3
Dependent Claim 210 words
A semiconductor device having enhanced thermal stability over a relatively wide temperature range and comprising: a diamond layer having a semiconducting active region therein and a drain region and a source region adjacent said semiconducting active region; an insulating layer adjacent said semiconducting active region; and gating means on said insulating layer for modulating said semiconductor active region so that the semiconductor device is an insulated-gate field effect transistor; said semiconducting active region including an intentional dopant of a first conductivity type and an unintentional impurity of a second conductivity type at respective concentrations to together produce at room temperature a predetermined compensated majority free carrier concentration of first conductivity type; and said intentional dopant concentration being relatively low at less than 1×10 16 cm -3 and supplying substantially all of the majority free carriers in said active region when conduction in said active region is dominated by majority carrier transport and not by minority carrier transport, and the unintentional impurity concentration being less than the intentional dopant concentration so that a difference between the intentional dopant concentration and the unintentional impurity concentration is less than 1000 times the predetermined compensated majority free carrier concentration to thereby enhance thermal stability for the semiconductor device over a relatively wide temperature range.
Claim 4
Dependent Claim 210 words
A semiconductor device having enhanced thermal stability over a relatively wide temperature range and comprising: a diamond layer having a semiconducting active region therein and a drain region and a source region adjacent said semiconducting active region; an insulating layer adjacent said semiconducting active region; and gating means on said insulating layer for modulating said semiconductor active region so that the semiconductor device is an insulated-gate field effect transistor; said semiconducting active region including an intentional dopant of a first conductivity type and an unintentional impurity of a second conductivity type at respective concentrations to together produce at room temperature a predetermined compensated majority free carrier concentration of first conductivity type; and said intentional dopant concentration being relatively low at less than 1×10 16 cm -3 and supplying substantially all of the majority free carriers in said active region when conduction in said active region is dominated by majority carrier transport and not by minority carrier transport, and the unintentional impurity concentration being less than the intentional dopant concentration so that a difference between the intentional dopant concentration and the unintentional impurity concentration is less than 1000 times the predetermined compensated majority free carrier concentration to thereby enhance thermal stability for the semiconductor device over a relatively wide temperature range.
Claim 5
Dependent Claim 186 words
A semiconductor device having enhanced thermal stability over a relatively wide temperature range and comprising: a wide bandgap semiconductor layer having a semiconducting active region therein and a drain region and a source region adjacent said semiconducting active region; an insulating layer adjacent said semiconducting active region; and gating means on said insulating layer for modulating said semiconductor active region so that the semiconductor device is an insulated-gate field effect transistor; said semiconducting active region including an intentional dopant of a first conductivity type and an unintentional impurity of a second conductivity type at respective concentrations to together produce at room temperature a compensated majority free carrier concentration of first conductivity type; and said intentional dopant concentration being relatively low at less than ×10 16 cm -3 and supplying substantially all the majority free carriers in said active region when conduction in said active region is dominated by majority carrier transport and not by minority carrier transport, to thereby enhance thermal stability for the semiconductor device over a relatively wide temperature range, wherein the unintentional impurity concentration is less than 0.1 times the intentional dopant concentration.
Claim 6
Dependent Claim 186 words
A semiconductor device having enhanced thermal stability over a relatively wide temperature range and comprising: a wide bandgap semiconductor layer having a semiconducting active region therein and a drain region and a source region adjacent said semiconducting active region; an insulating layer adjacent said semiconducting active region; and gating means on said insulating layer for modulating said semiconductor active region so that the semiconductor device is an insulated-gate field effect transistor; said semiconducting active region including an intentional dopant of a first conductivity type and an unintentional impurity of a second conductivity type at respective concentrations to together produce at room temperature a compensated majority free carrier concentration of first conductivity type; and said intentional dopant concentration being relatively low at less than ×10 16 cm -3 and supplying substantially all the majority free carriers in said active region when conduction in said active region is dominated by majority carrier transport and not by minority carrier transport, to thereby enhance thermal stability for the semiconductor device over a relatively wide temperature range, wherein the unintentional impurity concentration is less than 0.1 times the intentional dopant concentration.
Claim 7
Dependent Claim 153 words
An insulated-gate field effect transistor having enhanced thermal stability over a relatively wide temperature range, the insulated-gate field effect transistor comprising: a wide bandgap semiconductor layer comprising a semiconducting active region including an intentional dopant of a first conductivity type and an unintentional impurity of a second conductivity type at respective concentrations to together produce at room temperature a compensated majority free carrier concentration of first conductivity type, said intentional dopant concentration being relatively low at less than 1×10 16 cm-3 and supplying substantially all the majority free carriers in said active region when conduction in said active region is dominated by majority carrier transport and not by minority carrier transport; a source region and a drain region adjacent said active region; and gating means comprising an insulating region on said active region, for modulating said semiconducting active region, wherein the unintentional impurity concentration is less than 0.1 times the intentional dopant concentration.
Claim 8
Dependent Claim 153 words
An insulated-gate field effect transistor having enhanced thermal stability over a relatively wide temperature range, the insulated-gate field effect transistor comprising: a wide bandgap semiconductor layer comprising a semiconducting active region including an intentional dopant of a first conductivity type and an unintentional impurity of a second conductivity type at respective concentrations to together produce at room temperature a compensated majority free carrier concentration of first conductivity type, said intentional dopant concentration being relatively low at less than 1×10 16 cm-3 and supplying substantially all the majority free carriers in said active region when conduction in said active region is dominated by majority carrier transport and not by minority carrier transport; a source region and a drain region adjacent said active region; and gating means comprising an insulating region on said active region, for modulating said semiconducting active region, wherein the unintentional impurity concentration is less than 0.1 times the intentional dopant concentration.
Claim 9
Dependent Claim 20 words
A field effect transistor of claim 4, wherein said wide bandgap semiconductor has a bandgap energy greater than 1.5 eV.
Claim 10
Dependent Claim 21 words
A field effect transistor of claim 4, wherein the unintentional impurity concentration is less than 0.01 times the intentional dopant concentration.
Claim 11
Dependent Claim 25 words
A field effect transistor of claim 4, wherein said intentional dopant has an ionization activation energy greater than 150 meV in said semiconducting diamond layer.
Claim 12
Dependent Claim 33 words
A field effect transistor of claim 4, wherein said wide bandgap semiconductor is selected from the group consisting of diamond, IV-IV carbides, III-V nitrides and phosphides and II-VI selenides, tellurides, oxides and sulfides.
Claim 13
Dependent Claim 45 words
A field effect transistor of claim 4, wherein the unintentional impurity concentration is less than the intentional dopant concentration so that a difference between the intentional dopant concentration and the unintentional impurity concentration is less than 1000 times the free carrier concentration at room temperature.
Claim 14
Dependent Claim 45 words
A field effect transistor of claim 4, wherein the unintentional impurity concentration is less than the intentional dopant concentration so that a difference between the intentional dopant concentration and the unintentional impurity concentration is less than 500 times the free carrier concentration at room temperature.

References Cited (Backward Citations)

US3617975A Cited
US4963954A Cited
US5183530A Cited
US5278430A Cited
US5223721A Cited
US5252840A Cited
JPH0426172A Cited
US5162886A Cited
US5231301A Cited
US5289017A Cited
US5285089A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-07-16 2000-01-15 2000-07-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-07-16 2004-01-15 2004-07-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-07-16 2008-01-15 2008-07-16 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag