US5536667A
Expired / Lapsed
US
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Method for forming a gate electrode in a semiconductor device
Assignee: SK Hynix Inc
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Filing: 1995-05-15
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Granted: 1996-07-16
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Expires: 2015-05-15
Abstract
Abstract A method for forming a gate electrode in a semiconductor device is disclosed. An injection of the holes which moved from the control gate to a dielectric layer is suppressed since the control gate electrode is formed with a double layer structure composed of polysilicon-germanium and polysilicon. Accordingly, the data retention time is increased by increasing the energy barrier for a hole.
Inventors
- 👤 Byung J. Cho
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:06
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10B; H10B41/00; H10D30/60; H10D30/68; H10D30/6891; H10D64/00; H10D64/60; H10D64/66; H10D64/667; H10D64/668; H10P; H10P14/00; H10P14/20; H10P14/24; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P95/00; H10P95/90
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
162 words
A method for forming a gate electrode in a semiconductor device, comprising the steps of: forming a tunnel oxide layer on a silicon substrate; depositing a first polysilicon layer on said tunnel oxide layer and doping an impurity ion in said polysilicon to form a floating gate; sequentially forming a bottom oxide layer, a nitride layer and a top oxide layer on said floating gate to form an interpoly dielectric layer; depositing a polysilicon-germanium layer having a larger energy barrier than polysilicon for a hole on said interpoly dielectric layer to form a first portion of a control gate; depositing a second polysilicon layer on said first portion of the control gate and doping an impurity ion in said second polysilicon layer to form a second portion of the control gate; and sequentially patterning said first and second portions of the control gate, said interpoly dielectric layer, said floating gate and said tunnel oxide layer using a photolithography and dry etching process.
Claim 2
Independent Claim
162 words
A method for forming a gate electrode in a semiconductor device, comprising the steps of: forming a tunnel oxide layer on a silicon substrate; depositing a first polysilicon layer on said tunnel oxide layer and doping an impurity ion in said polysilicon to form a floating gate; sequentially forming a bottom oxide layer, a nitride layer and a top oxide layer on said floating gate to form an interpoly dielectric layer; depositing a polysilicon-germanium layer having a larger energy barrier than polysilicon for a hole on said interpoly dielectric layer to form a first portion of a control gate; depositing a second polysilicon layer on said first portion of the control gate and doping an impurity ion in said second polysilicon layer to form a second portion of the control gate; and sequentially patterning said first and second portions of the control gate, said interpoly dielectric layer, said floating gate and said tunnel oxide layer using a photolithography and dry etching process.
Claim 3
Dependent Claim
20 words
A method according to claim 1, wherein said polysilicon-germanium layer is deposited with a thickness of 200 to 1000 angstroms.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-16 | 2000-01-15 | 2000-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-16 | 2004-01-15 | 2004-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-16 | 2008-01-15 | 2008-07-16 | $7700.00 | Window Closed / Lapsed |