US4334292A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low voltage electrically erasable programmable read only memory
Assignee: International Business Machines Corp
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Filing: 1980-05-27
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Granted: 1982-06-08
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Expires: 2000-05-27
Abstract
Abstract An improved memory system is provided for charging and discharging a conductive plate such as a floating gate of a field effect transistor with a charge injector controlled by a low single polarity voltage pulse. In the system of the invention, the conductive plate may be a floating gate of a field effect transistor which also includes first and second or dual control gates. A single or double graded band gap layer, such as a silicon rich layer of silicon dioxide is disposed only between the floating gate and the first control gate forming a capacitor having a given capacitance with a larger capacitor disposed between the second control gate and the floating gate. These cells or transistors may be used in an array for storing for long periods of time, on the order of 10 years or more, binary digits of information representing a 0 or a 1 depending upon whether a charge is stored on the floating gate. When using these cells in a memory array, information may be written into or erased from each of the cells individually or a blanket erase may be employed for the entire or a selected section of the array. To write and to erase a cell, a low single polarity voltage is employed. Several embodiments of the invention are disclosed including one embodiment wherein the dual gates are located on one side of the floating gate, a second embodiment which uses a diffusion in a semiconductor substrate as one of the control gates and a third embodiment wherein one of the control gates is disposed on one side of, or above, the floating gate and the other control gate is disposed on the other side of, or below, the floating gate near the surface of the channel region of the transistor.
Inventors
- 👤 Harish N. Kotecha
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 02:36
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/682
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
84 words
A system comprising; a field effect transistor having a floating gate and first and second control gates, a charge injector having a graded band gap or stepped composition region disposed between said first control gate and said floating gate having a given capacitance value, a capacitor disposed between said second control gate and said floating gate having a capacitance value substantially greater than said given capacitance value, and means for applying control pulses to said control gates for controlling charge on said floating gate.
Claim 2
Independent Claim
84 words
A system comprising; a field effect transistor having a floating gate and first and second control gates, a charge injector having a graded band gap or stepped composition region disposed between said first control gate and said floating gate having a given capacitance value, a capacitor disposed between said second control gate and said floating gate having a capacitance value substantially greater than said given capacitance value, and means for applying control pulses to said control gates for controlling charge on said floating gate.
Claim 3
Independent Claim
92 words
A system comprising; a charge trapping layer, first and second electrodes, a charge injector having a graded band gap or stepped composition region and a given capacitance value disposed between said first electrode and said charge trapping layer, a capacitor having a capacitance value substantially larger than said given value disposed between said second electrode and said charge trapping layer, means for selectively applying voltage pulses to said first and second electrodes for controlling charge in said charge trapping layer, and means for detecting the charged condition of said charge trapping layer.
Claim 4
Independent Claim
92 words
A system comprising; a charge trapping layer, first and second electrodes, a charge injector having a graded band gap or stepped composition region and a given capacitance value disposed between said first electrode and said charge trapping layer, a capacitor having a capacitance value substantially larger than said given value disposed between said second electrode and said charge trapping layer, means for selectively applying voltage pulses to said first and second electrodes for controlling charge in said charge trapping layer, and means for detecting the charged condition of said charge trapping layer.
Claim 5
Dependent Claim
109 words
A memory system comprising; a field effect transistor having a floating gate, first and second control gates and source and drain regions defining a channel region, a charge injector system including a silicon rich insulating layer disposed between said first control gate and said floating gate, said charge injector having a given capacitance value, a capacitor having a capacitance value substantially larger than said given capacitance value disposed between said second gate and said floating gate, means for selectively applying voltage pulses to said control gates for controlling charge on said floating gate, and means including said drain, source and channel regions for detecting charge on said floating gate.
Claim 6
Dependent Claim
109 words
A memory system comprising; a field effect transistor having a floating gate, first and second control gates and source and drain regions defining a channel region, a charge injector system including a silicon rich insulating layer disposed between said first control gate and said floating gate, said charge injector having a given capacitance value, a capacitor having a capacitance value substantially larger than said given capacitance value disposed between said second gate and said floating gate, means for selectively applying voltage pulses to said control gates for controlling charge on said floating gate, and means including said drain, source and channel regions for detecting charge on said floating gate.
Claim 7
Dependent Claim
101 words
A switching system comprising; a semiconductor substrate, first and second electrodes, a conductive plate, a first thin insulating layer disposed between said conductive plate and said substrate, a second thin insulating layer disposed between said conductive plate and said first electrode forming a capacitor having a given capacitance value, a charge injector system having a graded band gap or stepped composition region disposed between said conductive plate and said second electrode exhibiting a capacitance having a value substantially less than said given capacitance value, and means for selectively applying voltage pulses to said electrodes for controlling charges on said conductive plate.
Claim 8
Dependent Claim
101 words
A switching system comprising; a semiconductor substrate, first and second electrodes, a conductive plate, a first thin insulating layer disposed between said conductive plate and said substrate, a second thin insulating layer disposed between said conductive plate and said first electrode forming a capacitor having a given capacitance value, a charge injector system having a graded band gap or stepped composition region disposed between said conductive plate and said second electrode exhibiting a capacitance having a value substantially less than said given capacitance value, and means for selectively applying voltage pulses to said electrodes for controlling charges on said conductive plate.
Claim 9
Dependent Claim
139 words
A memory system comprising; an array having a plurality of cells, each cell including a transistor having first and second control gates, a floating gate and source and drain regions, a charge injector having a graded band gap or stepped composition region and a given capacitance value disposed between said first control gate and said floating gate and a capacitor having a capacitance value substantially greater than said given capacitance value disposed between said second control gate and said floating gate, a word line decoder and driver circuit coupled to the second control gate of each of said transistors, a write/erase line decoder and driver circuit coupled to the first control gate of each of said transistors, and a bit line decoder, precharge and sense amplifier circuit coupled to the source and drain regions of each of said transistors.
Claim 10
Dependent Claim
139 words
A memory system comprising; an array having a plurality of cells, each cell including a transistor having first and second control gates, a floating gate and source and drain regions, a charge injector having a graded band gap or stepped composition region and a given capacitance value disposed between said first control gate and said floating gate and a capacitor having a capacitance value substantially greater than said given capacitance value disposed between said second control gate and said floating gate, a word line decoder and driver circuit coupled to the second control gate of each of said transistors, a write/erase line decoder and driver circuit coupled to the first control gate of each of said transistors, and a bit line decoder, precharge and sense amplifier circuit coupled to the source and drain regions of each of said transistors.
Claim 11
Independent Claim
88 words
A system comprising; a field effect transistor having a floating gate and first and second control gates, a charge injector including a graded or stepped composition region disposed between said first control gate and said floating gate adjacent said first control gate having a given capacitance value, a capacitor disposed between said second control gate and said floating gate having a capacitance value several times that of said given capacitance value, and means for applying control pulses to said control gates for controlling charge on said floating gate.
Claim 12
Independent Claim
88 words
A system comprising; a field effect transistor having a floating gate and first and second control gates, a charge injector including a graded or stepped composition region disposed between said first control gate and said floating gate adjacent said first control gate having a given capacitance value, a capacitor disposed between said second control gate and said floating gate having a capacitance value several times that of said given capacitance value, and means for applying control pulses to said control gates for controlling charge on said floating gate.
Claim 13
Independent Claim
96 words
A system comprising; a charge trapping layer, first and second electrodes, a charge injector including a graded or stepped composition region having a given capacitance value disposed between said first electrode and said charge trapping layer adjacent said first electrode, a capacitor having a capacitance value several times that of said given capacitance value disposed between said second electrode and said charge trapping layer, means for selectively applying voltage pulses to said first and second electrodes for controlling charge in said charge trapping layer, and means for detecting the charged condition of said charge trapping layer.
Claim 14
Independent Claim
96 words
A system comprising; a charge trapping layer, first and second electrodes, a charge injector including a graded or stepped composition region having a given capacitance value disposed between said first electrode and said charge trapping layer adjacent said first electrode, a capacitor having a capacitance value several times that of said given capacitance value disposed between said second electrode and said charge trapping layer, means for selectively applying voltage pulses to said first and second electrodes for controlling charge in said charge trapping layer, and means for detecting the charged condition of said charge trapping layer.
Claim 15
Dependent Claim
23 words
A system as set forth in claim 1 wherein said capacitor has a capacitance value several times that of said given capacitance value.
Claim 16
Dependent Claim
24 words
A system as set forth in claim 6 wherein said injector includes an insulator having graded or stepped composition regions near opposite surfaces thereof.
Claim 17
Dependent Claim
35 words
A system as set forth in claim 9 wherein a first of said regions is disposed adjacent to said first control gate and a second of said regions is disposed adjacent to said floating gate.
Claim 18
Dependent Claim
28 words
A system as set forth in claim 8 wherein said injector includes a silicon dioxide layer having a graded or stepped composition region adjacent said first control gate.
Claim 19
Dependent Claim
14 words
A system as set forth in claim 11 wherein said composition region includes silicon.
Claim 20
Dependent Claim
16 words
A system as set forth in claim 10 wherein said first and second regions include silicon.
Claim 21
Dependent Claim
24 words
A system as set forth in claim 6 wherein said first and second control gates are disposed on one side of said floating gate.
Claim 22
Dependent Claim
40 words
A system as set forth in claim 6 wherein one of said control gates is disposed on one side of said floating gate and the other of said control gates is disposed on the opposite side of said floating gate.
Claim 23
Dependent Claim
22 words
A system as set forth in claim 15 wherein one of said control gates is a diffusion region of a semiconductor substrate.
Claim 24
Dependent Claim
23 words
A system as set forth in claim 2 wherein said capacitor has a capacitance value several times that of said given capacitance value.
Claim 25
Dependent Claim
24 words
A system as set forth in claim 7 wherein said injector includes an insulator having graded or stepped composition regions near opposite surfaces thereof.
Claim 26
Dependent Claim
35 words
A system as set forth in claim 18 wherein a first of said regions is disposed adjacent to said first electrode and a second of said regions is disposed adjacent to said charge trapping layer.
Claim 27
Dependent Claim
15 words
A system as set forth in claim 19 wherein each of said regions includes silicon.
Claim 28
Dependent Claim
25 words
A system as set forth in claim 19 wherein said first and second electrodes are disposed on the same side of said charge trappping layer.
Claim 29
Dependent Claim
43 words
A system as set forth in claim 19 wherein one of said first and second electrodes is disposed on one side of said charge trapping layer and the other of said electrodes is disposed on the opposite side of said charge trapping layer.
Claim 30
Dependent Claim
18 words
A system as set forth in claim 22 wherein one of said electrodes is a diffused semiconductor region.
Claim 31
Dependent Claim
25 words
A memory system as set forth in claim 3 wherein said first and second control gates are disposed on one side of said floating gate.
Claim 32
Dependent Claim
38 words
A memory system as set forth in claim 3 wherein one of said control gates is disposed on one side of said floating gate and the other of said control gates is disposed on the other side thereof.
Claim 33
Dependent Claim
31 words
A memory system as set forth in claim 25 wherein one of said control gates is made of polysilicon and the other of said control gates is a diffused semiconductor region.
Claim 34
Dependent Claim
54 words
A switching system as set forth in claim 4 wherein said graded band gap or stepped composition region of said injector system includes an insulator having spaced apart first and second silicon rich regions, said first region being disposed adjacent to said second electrode and said second region being disposed adjacent said conductive plate.
References Cited (Backward Citations)
US3825946A
Cited
US4161039A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-06-07 | 1985-12-07 | 1986-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-06-07 | 1989-12-07 | 1990-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-06-07 | 1993-12-07 | 1994-06-08 | $7700.00 | Window Closed / Lapsed |