Patent US5535343A successfully refreshed from Google Patents.
US5535343A
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Method and apparatus for generating write signals
Assignee: Intel Corp
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Filing: 1994-03-07
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Granted: 1996-07-09
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Expires: 2014-03-07
Abstract
Abstract A write pulse generator circuit which uses first and second flip-flop circuits adapted to provide output pulses to an exclusive OR gate to generate write pulses. The circuit includes apparatus for toggling the first flip-flop in response to a rising edge of a clock pulse, and apparatus for toggling the second flip-flop in response to a falling edge of the clock pulse. By utilizing opposite phase output signals from the flip-flops, tuning of the circuit for particular operating conditions and for particular processes is eliminated.
Inventors
- 👤 Jerry Verseput
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 02:46
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/405
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
178 words
An apparatus for generating a write pulse signal, comprising: a first flip flop providing a first flip flop output signal in response to a clock signal and a first flip flop input signal; a first multiplexor for selecting the first flip flop input signal from one of the first flip flop output signal and a complement of the first flip flop output signal in response to a write enable signal; a second flip flop providing a second flip flop output signal in response to a complement of the clock signal and a second flip flop input signal; a second multiplexor for selecting the second flip flop input signal from one of the second flip flop output signal and a complement of the second flip flop output signal in response to a control signal; a third flip flop providing the control signal in response to the clock signal and the write enable signal; and a logic gate generating the write pulse signal from the first flip flop output signal and the complement of the second flip flop output signal.
Claim 2
Independent Claim
178 words
An apparatus for generating a write pulse signal, comprising: a first flip flop providing a first flip flop output signal in response to a clock signal and a first flip flop input signal; a first multiplexor for selecting the first flip flop input signal from one of the first flip flop output signal and a complement of the first flip flop output signal in response to a write enable signal; a second flip flop providing a second flip flop output signal in response to a complement of the clock signal and a second flip flop input signal; a second multiplexor for selecting the second flip flop input signal from one of the second flip flop output signal and a complement of the second flip flop output signal in response to a control signal; a third flip flop providing the control signal in response to the clock signal and the write enable signal; and a logic gate generating the write pulse signal from the first flip flop output signal and the complement of the second flip flop output signal.
Claim 3
Dependent Claim
22 words
The apparatus of claim 1 wherein at least one of the first, second, and third flip flops is a D flip flop.
Claim 4
Dependent Claim
14 words
The apparatus of claim 1 wherein the logic gate is an exclusive OR gate.
Claim 5
Dependent Claim
225 words
A computer system comprising: a processor; a main memory; a first bus associated with the processor and main memory; a second bus; a bridge circuit having a plurality of buffers for storing information being transferred between the first and second bus; and a write pulse signal generator for controlling writing to the plurality of buffers comprising: a first flip flop providing a first flip flop output signal in response to a clock signal and a first flip flop input signal; a first multiplexor for selecting the first flip flop input signal from one of the first flip flop output signal and a complement of the first flip flop output signal in response to a write enable signal; a second flip flop providing a second flip flop output signal in response to a complement of the clock signal and a second flip flop input signal; a second multiplexor for selecting the second flip flop input signal from one of the second flip flop output signal and a complement of the second flip flop output signal in response to a control signal; a third flip flop providing the control signal in response to the clock signal and the write enable signal; and a logic gate generating the write pulse signal from the first flip flop output signal and the complement of the second flip flop output signal.
Claim 6
Dependent Claim
225 words
A computer system comprising: a processor; a main memory; a first bus associated with the processor and main memory; a second bus; a bridge circuit having a plurality of buffers for storing information being transferred between the first and second bus; and a write pulse signal generator for controlling writing to the plurality of buffers comprising: a first flip flop providing a first flip flop output signal in response to a clock signal and a first flip flop input signal; a first multiplexor for selecting the first flip flop input signal from one of the first flip flop output signal and a complement of the first flip flop output signal in response to a write enable signal; a second flip flop providing a second flip flop output signal in response to a complement of the clock signal and a second flip flop input signal; a second multiplexor for selecting the second flip flop input signal from one of the second flip flop output signal and a complement of the second flip flop output signal in response to a control signal; a third flip flop providing the control signal in response to the clock signal and the write enable signal; and a logic gate generating the write pulse signal from the first flip flop output signal and the complement of the second flip flop output signal.
Claim 7
Dependent Claim
22 words
The apparatus of claim 4 wherein at least one of the first, second, and third flip flops is a D flip flop.
Claim 8
Dependent Claim
14 words
The apparatus of claim 4 wherein the logic gate is an exclusive OR gate.
Claim 9
Independent Claim
176 words
An apparatus for generating a write pulse signal, comprising: a first flip flop providing a first flip flop output signal in response to a clock signal and a first flip flop input signal; a first multiplexor for selecting the first flip flop input signal from one of the first flip flop output signal and a complement of the first flip flop output signal in response to a write enable signal; a second flip flop providing a second flip flop output signal in response to a delayed clock signal and a second flip flop input signal; a second multiplexor for selecting the second flip flop input signal from one of the second flip flop output signal and a complement of the second flip flop output signal in response to a control signal; a third flip flop providing the control signal in response to the clock signal and the write enable signal; and a logic gate generating the write pulse signal from the first flip flop output signal and the complement of the second flip flop output signal.
Claim 10
Independent Claim
176 words
An apparatus for generating a write pulse signal, comprising: a first flip flop providing a first flip flop output signal in response to a clock signal and a first flip flop input signal; a first multiplexor for selecting the first flip flop input signal from one of the first flip flop output signal and a complement of the first flip flop output signal in response to a write enable signal; a second flip flop providing a second flip flop output signal in response to a delayed clock signal and a second flip flop input signal; a second multiplexor for selecting the second flip flop input signal from one of the second flip flop output signal and a complement of the second flip flop output signal in response to a control signal; a third flip flop providing the control signal in response to the clock signal and the write enable signal; and a logic gate generating the write pulse signal from the first flip flop output signal and the complement of the second flip flop output signal.
Claim 11
Dependent Claim
15 words
The apparatus of claim 7 wherein the delayed clock signal is an inverted clock signal.
Claim 12
Dependent Claim
25 words
The apparatus of claim 7 wherein the delayed clock signal is the clock signal delayed by approximately one-half of a period of a clock cycle.
Claim 13
Dependent Claim
22 words
The apparatus of claim 7 wherein at least one of the first, second, and third flip flops is a D flip flop.
Claim 14
Dependent Claim
14 words
The apparatus of claim 7 wherein the logic gate is an exclusive OR gate.
Claim 15
Dependent Claim
223 words
A computer system comprising: a processor; a main memory; a first bus associated with the processor and main memory; a second bus; a bridge circuit having a plurality of buffers for storing information being transferred between the first and second bus; and a write pulse signal generator for controlling writing to the plurality of buffers comprising: a first flip flop providing a first flip flop output signal in response to a clock signal and a first flip flop input signal; a first multiplexor for selecting the first flip flop input signal from one of the first flip flop output signal and a complement of the first flip flop output signal in response to a write enable signal; a second flip flop providing a second flip flop output signal in response to a delayed clock signal and a second flip flop input signal; a second multiplexor for selecting the second flip flop input signal from one of the second flip flop output signal and a complement of the second flip flop output signal in response to a control signal; a third flip flop providing the control signal in response to the clock signal and the write enable signal; and a logic gate generating the write pulse signal from the first flip flop output signal and the complement of the second flip flop output signal.
Claim 16
Dependent Claim
223 words
A computer system comprising: a processor; a main memory; a first bus associated with the processor and main memory; a second bus; a bridge circuit having a plurality of buffers for storing information being transferred between the first and second bus; and a write pulse signal generator for controlling writing to the plurality of buffers comprising: a first flip flop providing a first flip flop output signal in response to a clock signal and a first flip flop input signal; a first multiplexor for selecting the first flip flop input signal from one of the first flip flop output signal and a complement of the first flip flop output signal in response to a write enable signal; a second flip flop providing a second flip flop output signal in response to a delayed clock signal and a second flip flop input signal; a second multiplexor for selecting the second flip flop input signal from one of the second flip flop output signal and a complement of the second flip flop output signal in response to a control signal; a third flip flop providing the control signal in response to the clock signal and the write enable signal; and a logic gate generating the write pulse signal from the first flip flop output signal and the complement of the second flip flop output signal.
Claim 17
Dependent Claim
15 words
The apparatus of claim 12 wherein the delayed clock signal is an inverted clock signal.
Claim 18
Dependent Claim
23 words
The apparatus of claim 12 wherein the delayed clock signal is the clock signal delayed by approximately one-half of a clock signal period.
Claim 19
Dependent Claim
22 words
The apparatus of claim 12 wherein at least one of the first, second, and third flip flops is a D flip flop.
Claim 20
Dependent Claim
14 words
The apparatus of claim 12 wherein the logic gate is an exclusive OR gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-09 | 2000-01-08 | 2000-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-09 | 2004-01-08 | 2004-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-09 | 2008-01-08 | 2008-07-09 | $7700.00 | Window Closed / Lapsed |