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US5535154A
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Semiconductor memory device with CMOS-inverter storage cells
Assignee: NEC Corp
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Filing: 1994-12-22
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Granted: 1996-07-09
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Expires: 2014-12-22
Abstract
Abstract A semiconductor memory device in which each storage cell can maintain its content or data value stored therein even if power is lost, and the content or data value thus maintained can be produced when power is on. Each storage cell has first and second CMOS inverters constituting a flip-flop circuit. The first inverter is composed of a first MOS driver transistor and a first thin-film load transistor. The second inverter is composed of a second MOS driver transistor and a second thin-film load transistor. The first and second load transistors have control gate electrodes and ferroelectric PZT films, respectively. The PZT films are dielectrically polarized by voltages applied to the control gate electrodes, so that the threshold voltage difference is generated between the first and second thin-film transistors. Due to the threshold voltage difference, the preceding content or state of the cell is maintained, and then, it can be reproduced when power is supplied again.
Inventors
- 👤 Junji Kiyono
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:16
CPC Classifications
G; G11; G11C; G11C14/00; H; H10; H10B; H10B10/00; H10B10/12; H10B10/125; H10B69/00
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
334 words
A semiconductor memory device containing a plurality of storage cells, each of said cells comprising: a first CMOS inverter having a first input end and a first output end; a second CMOS inverter having a second input end and a second output end; said first input end being connected with said second output end and said second input end being connected with said first output end; said first inverter and said second inverter constituting a flip-flop circuit; said first CMOS inverter being composed of a first MOS driver transistor of a first conductivity type and a first pair of thin-film transistors of a second conductivity type opposite in polarity to said first conductivity type; and said first pair of thin-film transistors having a first pair of source/drain regions, a first channel region formed between said first pair of source/drain regions, a first gate electrode formed to be opposite to said first channel region through a first gate insulator film, and a first control electrode formed to be opposite to said first channel region through a first ferroelectric insulator film; said second CMOS inverter being composed of a second MOS driver transistor of a first conductivity type and a second pair of thin-film transistors of a second conductivity type opposite in polarity to said first conductivity type; said second pair of thin-film transistors having a second pair of source/drain regions, a second channel region formed between said second pair of source/drain regions, a second gate electrode formed to be opposite to said second channel region through a second gate insulator film, and a second control electrode formed to be opposite to said second channel region through a second ferroelectric insulator film; wherein said first and second ferroelectric insulator films are dielectrically polarized by applying voltages to said first and second control electrodes, so that a threshold voltage difference is generated between said first and second pairs of thin-film transistors; and wherein a content of said storage cell is maintained due to said threshold voltage difference.
Claim 2
Dependent Claim
334 words
A semiconductor memory device containing a plurality of storage cells, each of said cells comprising: a first CMOS inverter having a first input end and a first output end; a second CMOS inverter having a second input end and a second output end; said first input end being connected with said second output end and said second input end being connected with said first output end; said first inverter and said second inverter constituting a flip-flop circuit; said first CMOS inverter being composed of a first MOS driver transistor of a first conductivity type and a first pair of thin-film transistors of a second conductivity type opposite in polarity to said first conductivity type; and said first pair of thin-film transistors having a first pair of source/drain regions, a first channel region formed between said first pair of source/drain regions, a first gate electrode formed to be opposite to said first channel region through a first gate insulator film, and a first control electrode formed to be opposite to said first channel region through a first ferroelectric insulator film; said second CMOS inverter being composed of a second MOS driver transistor of a first conductivity type and a second pair of thin-film transistors of a second conductivity type opposite in polarity to said first conductivity type; said second pair of thin-film transistors having a second pair of source/drain regions, a second channel region formed between said second pair of source/drain regions, a second gate electrode formed to be opposite to said second channel region through a second gate insulator film, and a second control electrode formed to be opposite to said second channel region through a second ferroelectric insulator film; wherein said first and second ferroelectric insulator films are dielectrically polarized by applying voltages to said first and second control electrodes, so that a threshold voltage difference is generated between said first and second pairs of thin-film transistors; and wherein a content of said storage cell is maintained due to said threshold voltage difference.
Claim 3
Dependent Claim
33 words
The device as claimed in claim 1, wherein said first gate electrode and said first control electrode are coupled together and said second gate electrode and said second control electrode are coupled together.
Claim 4
Dependent Claim
56 words
The device as claimed in claim 1, wherein said first gate electrode and said first control electrode are not coupled together, said first control electrode being applied with a control voltage; and wherein said second gate electrode and said second control electrode are not coupled together, said second control electrode being applied with a control voltage.
Claim 5
Dependent Claim
24 words
The device as claimed in claim 1, wherein said first and second control electrodes are coupled together to be applied with a control voltage.
Claim 6
Dependent Claim
38 words
The device as claimed in claim 1, wherein dielectric polarization of said first and second ferroelectric films are generated by varying a supply voltage to said storage cell after a data value is stored in said storage cell.
Claim 7
Dependent Claim
40 words
The device as claimed in claim 1, wherein dielectric polarization of said first and second ferroelectric films are generated by varying voltages applied to said first and second control electrodes after a data value is stored in said storage cell.
Claim 8
Dependent Claim
75 words
The device as claimed in claim 1, wherein said first gate electrode and said first control electrode of said first pair of thin-film transistors are placed at each side of said first channel region of said first pair of thin-film transistors, and said second gate electrode and said second control electrode of said second pair of thin-film transistors are placed at each side of said second channel region of said second pair of thin-film transistors.
Claim 9
Dependent Claim
18 words
The device as claimed in claim 1, wherein said first and second ferroelectric films are made of PZT.
Claim 10
Dependent Claim
299 words
In a semiconductor memory device containing a plurality of storage cells, each of said cells comprising: a first CMOS inverter having a first input end and a first output end; a second CMOS inverter having a second input end and a second output end; said first input end being connected with said second output end and said second input end being connected with said first output end; said first inverter and said second inverter constituting a flip-flop circuit; wherein said first CMOS inverter contains a first pair of thin-film transistors and said second CMOS inverter contains a second pair of thin-film transistors; and wherein said first pair of thin-film transistors having a first channel region formed between a first pair of source/drain regions, a first gate insulator film formed at one side of said first channel region, a first gate electrode formed on said first gate insulator film, a first ferroelectric insulator film formed at another side of said first channel region, and a first control electrode formed on said first ferroelectric insulator film; and wherein said second pair of thin-film transistors having a second channel region formed between a second first pair of source/drain regions, a second gate insulator film formed at one side of said second channel region, a second gate electrode formed on said second gate insulator film, a second ferroelectric insulator film formed at another side of said second channel region, and a second control electrode formed on said second ferroelectric insulator film; and wherein said first and second ferroelectric insulator films are dielectrically polarized by applying voltages to said first and second control electrodes, so that a threshold voltage difference is generated between said first and second pairs of thin-film transistors, maintaining a content of said storage cell due to said threshold voltage difference.
Claim 11
Dependent Claim
299 words
In a semiconductor memory device containing a plurality of storage cells, each of said cells comprising: a first CMOS inverter having a first input end and a first output end; a second CMOS inverter having a second input end and a second output end; said first input end being connected with said second output end and said second input end being connected with said first output end; said first inverter and said second inverter constituting a flip-flop circuit; wherein said first CMOS inverter contains a first pair of thin-film transistors and said second CMOS inverter contains a second pair of thin-film transistors; and wherein said first pair of thin-film transistors having a first channel region formed between a first pair of source/drain regions, a first gate insulator film formed at one side of said first channel region, a first gate electrode formed on said first gate insulator film, a first ferroelectric insulator film formed at another side of said first channel region, and a first control electrode formed on said first ferroelectric insulator film; and wherein said second pair of thin-film transistors having a second channel region formed between a second first pair of source/drain regions, a second gate insulator film formed at one side of said second channel region, a second gate electrode formed on said second gate insulator film, a second ferroelectric insulator film formed at another side of said second channel region, and a second control electrode formed on said second ferroelectric insulator film; and wherein said first and second ferroelectric insulator films are dielectrically polarized by applying voltages to said first and second control electrodes, so that a threshold voltage difference is generated between said first and second pairs of thin-film transistors, maintaining a content of said storage cell due to said threshold voltage difference.
Claim 12
Dependent Claim
33 words
The device as claim in claim 9, wherein said first gate electrode and said first control electrode are coupled together and said second gate electrode and said second control electrode are coupled together.
Claim 13
Dependent Claim
56 words
The device as claimed in claim 9, wherein said first gate electrode and said first control electrode are not coupled together, said first control electrode being applied with a control voltage; and wherein said second gate electrode and said second control electrode are not coupled together, said second control electrode being applied with a control voltage.
Claim 14
Dependent Claim
24 words
The device as claimed in claim 9, wherein said first and second control electrodes are coupled together to be applied with a control voltage.
Claim 15
Dependent Claim
38 words
The device as claimed in claim 9, wherein dielectric polarization of said first and second ferroelectric films are generated by varying a supply voltage to said storage cell after a data value is stored in said storage cell.
Claim 16
Dependent Claim
40 words
The device as claimed in claim 9, wherein dielectric polarization of said first and second ferroelectric films are generated by varying voltages applied to said first and second control electrodes after a data value is stored in said storage cell.
Claim 17
Dependent Claim
75 words
The device as claimed in claim 9, wherein said first gate electrode and said first control electrode of said first pair of thin-film transistors are placed at each side of said first channel region of said first pair of thin-film transistors, and said second gate electrode and said second control electrode of said second pair of thin-film transistors are placed at each side of said second channel region of said second pair of thin-film transistors.
Claim 18
Dependent Claim
18 words
The device as claimed in claim 9, wherein said first and second ferroelectric films are made of PZT.
References Cited (Backward Citations)
US5361224A
Cited
US5426315A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1999-07-09 | 2000-01-08 | 2000-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-09 | 2004-01-08 | 2004-07-09 | $3760.00 | Window Closed / Lapsed |
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