Patent US5534723A successfully refreshed from Google Patents.
US5534723A
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Semiconductor integrated circuit device having output and internal circuit MISFETS
Assignee: Micron Memory Japan Ltd
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Filing: 1995-04-27
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Granted: 1996-07-09
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Expires: 2015-04-27
Abstract
Abstract Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implantation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.
Inventors
- 👤 Hidetoshi Iwai
- 👤 Kazumichi Mitsusada
- 👤 Masamichi Ishihara
- 👤 Tetsuro Matsumoto
- 👤 Kazuyuki Miyazawa
- 👤 Hisao Katto
- 👤 Kousuke Okuyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:01
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10D; H10D30/00; H10D30/60; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0184; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856; H10D89/00; H10D89/60; H10D89/601; H10D89/811
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
273 words
A semiconductor integrated circuit device, comprising: an output pad formed on a semiconductor substrate; a first output MISFET having a first gate insulating film on said semiconductor substrate and a first gate electrode, with opposed edges, on said first gate insulating film, and further having source and drain regions and a first channel forming region in said semiconductor substrate; and a first MISFET having a second gate insulating film on said semiconductor substrate and a second gate electrode, with opposed edges, on said second gate insulating film, and further having source and drain regions and a second channel forming region in said semiconductor substrate, said drain region of said first MISFET including a first doped subregion of relatively high impurity concentration and a second doped subregion of relatively low impurity concentration, said second doped subregion being formed between said first doped subregion and said second channel forming region, said source and drain regions of said first MISFET being of a same conductivity type as said source and drain regions of said first output MISFET, said first MISFET being included in an internal circuit of the semiconductor integrated circuit device, said source region of said first output MISFET being electrically connected to a ground potential, and said drain region of said first output MISFET being electrically connected to said output pad, wherein a backward breakdown voltage at a pn-junction between said semiconductor substrate and said drain region of said first output MISFET at a drain edge thereof is lower than a backward breakdown voltage at a pn-junction between said semiconductor substrate and said drain region of said first MISFET at a drain edge thereof.
Claim 2
Dependent Claim
273 words
A semiconductor integrated circuit device, comprising: an output pad formed on a semiconductor substrate; a first output MISFET having a first gate insulating film on said semiconductor substrate and a first gate electrode, with opposed edges, on said first gate insulating film, and further having source and drain regions and a first channel forming region in said semiconductor substrate; and a first MISFET having a second gate insulating film on said semiconductor substrate and a second gate electrode, with opposed edges, on said second gate insulating film, and further having source and drain regions and a second channel forming region in said semiconductor substrate, said drain region of said first MISFET including a first doped subregion of relatively high impurity concentration and a second doped subregion of relatively low impurity concentration, said second doped subregion being formed between said first doped subregion and said second channel forming region, said source and drain regions of said first MISFET being of a same conductivity type as said source and drain regions of said first output MISFET, said first MISFET being included in an internal circuit of the semiconductor integrated circuit device, said source region of said first output MISFET being electrically connected to a ground potential, and said drain region of said first output MISFET being electrically connected to said output pad, wherein a backward breakdown voltage at a pn-junction between said semiconductor substrate and said drain region of said first output MISFET at a drain edge thereof is lower than a backward breakdown voltage at a pn-junction between said semiconductor substrate and said drain region of said first MISFET at a drain edge thereof.
Claim 3
Dependent Claim
21 words
A semiconductor integrated circuit device according to claim 1, wherein said first output MISFET and said first MISFET are n-channel MISFETs.
Claim 4
Dependent Claim
60 words
A semiconductor integrated circuit device according to claim 1, further comprising: a second output MISFET having a third gate insulating film on said semiconductor substrate and a third gate electrode on said third gate insulating film, and further having source and drain regions in said semiconductor substrate, said second output MISFET and said first output MISFET being connected in series.
Claim 5
Dependent Claim
42 words
A semiconductor integrated circuit device according to claim 3, wherein said second gate electrode is electrically connected to said first gate electrode, and wherein said first output MISFET and said second output MISFET are an n-channel MISFET and a p-channel MISFET, respectively.
Claim 6
Dependent Claim
69 words
A semiconductor integrated circuit device according to claim 3, further comprising: a second MISFET having a fourth gate insulating film on said semiconductor substrate and a fourth gate electrode on said fourth gate insulating film, and further having source and drain regions in said semiconductor substrate, said first MISFET and second MISFET being connected in series, said source region of said first MISFET being electrically connected to ground potential.
Claim 7
Dependent Claim
24 words
A semiconductor integrated circuit device according to claim 5, wherein said first MISFET, said first output MISFET, and said second MISFET are n-channel MISFETs.
Claim 8
Dependent Claim
80 words
A semiconductor integrated circuit device according to claim 3, further comprising: a second MISFET having a fourth gate insulating film on said semiconductor substrate and a fourth gate electrode on said fourth gate insulating film, and further having source and drain regions in said semiconductor substrate. said source region of said second MISFET being electrically connected to a ground potential, said drain region of said second MISFET being electrically connected to said first gate electrode of said first output MISFET.
Claim 9
Dependent Claim
21 words
A semiconductor integrated circuit device according to claim 7, wherein said second MISFET and said first output MISFET are n-channel MISFETs.
Claim 10
Dependent Claim
359 words
A semiconductor integrated circuit device, comprising: an output pad formed on a semiconductor substrate; a first output MISFET having a first gate insulating film on said semiconductor substrate and a first gate electrode, with opposed edges, on said first gate insulating film, and further having source and drain regions and a first channel forming region in said semiconductor substrate; a second output MISFET having a second gate insulating film on said semiconductor substrate and a second gate electrode, with opposed edges, on said second gate insulating film, and further having source and drain regions and a second channel forming region in said semiconductor substrate; and a first MISFET having a third gate insulating film on said semiconductor substrate and a third gate electrode, with opposed edges, on said third gate insulating film, and further having source and drain regions and a third channel forming region in said semiconductor substrate, said drain region of said first MISFET including a first doped subregion of relatively high impurity concentration and a second doped subregion of relatively low impurity concentration, said second doped subregion being formed between said first doped subregion and said third channel forming region, said source and drain regions of said first MISFET being of a same conductivity type as said source and drain regions of said first and second output MISFETs, said first MISFET being including in an internal circuit of the semiconductor integrated circuit device, said first output MISFET and said second output MISFET being included in a final stage of an output buffer circuit and being connected in series, said source region of said first output MISFET being electrically connected to a ground potential, and said drain region of said first output MISFET being electrically connected to both said output pad and one of said source and drain regions of said second output MISFET, wherein a backward breakdown voltage at a pn-junction between said semiconductor substrate and said drain region of said first output MISFET at a drain edge thereof is lower than a backward breakdown voltage at a pn-junction between said semiconductor substrate and said drain region of said first MISFET at a drain edge thereof.
Claim 11
Dependent Claim
359 words
A semiconductor integrated circuit device, comprising: an output pad formed on a semiconductor substrate; a first output MISFET having a first gate insulating film on said semiconductor substrate and a first gate electrode, with opposed edges, on said first gate insulating film, and further having source and drain regions and a first channel forming region in said semiconductor substrate; a second output MISFET having a second gate insulating film on said semiconductor substrate and a second gate electrode, with opposed edges, on said second gate insulating film, and further having source and drain regions and a second channel forming region in said semiconductor substrate; and a first MISFET having a third gate insulating film on said semiconductor substrate and a third gate electrode, with opposed edges, on said third gate insulating film, and further having source and drain regions and a third channel forming region in said semiconductor substrate, said drain region of said first MISFET including a first doped subregion of relatively high impurity concentration and a second doped subregion of relatively low impurity concentration, said second doped subregion being formed between said first doped subregion and said third channel forming region, said source and drain regions of said first MISFET being of a same conductivity type as said source and drain regions of said first and second output MISFETs, said first MISFET being including in an internal circuit of the semiconductor integrated circuit device, said first output MISFET and said second output MISFET being included in a final stage of an output buffer circuit and being connected in series, said source region of said first output MISFET being electrically connected to a ground potential, and said drain region of said first output MISFET being electrically connected to both said output pad and one of said source and drain regions of said second output MISFET, wherein a backward breakdown voltage at a pn-junction between said semiconductor substrate and said drain region of said first output MISFET at a drain edge thereof is lower than a backward breakdown voltage at a pn-junction between said semiconductor substrate and said drain region of said first MISFET at a drain edge thereof.
Claim 12
Dependent Claim
25 words
A semiconductor integrated circuit device according to claim 9, wherein said first output MISFET, said second output MISFET and said first MISFET are n-channel MISFETs.
Claim 13
Dependent Claim
79 words
A semiconductor integrated circuit device according to claim 9, further comprising: a second MISFET having a fourth gate insulating film on said semiconductor substrate and a fourth gate electrode on said fourth gate insulating film, and further having source and drain regions in said semiconductor substrate, said first MISFET and said second MISFET being connected in series, said source region of said first MISFET and said source region of said first output MISFET being electrically connected to ground potential.
Claim 14
Dependent Claim
80 words
A semiconductor integrated circuit device according to claim 9, further comprising: a second MISFET having a fourth gate insulating film on said semiconductor substrate and a fourth gate electrode on said fourth gate insulating film, and further having source and drain regions in said semiconductor substrate, said source region of said second MISFET being electrically connected to a ground potential. said drain region of said second MISFET being electrically connected to said first gate electrode of said first output MISFET.
Claim 15
Dependent Claim
21 words
A semiconductor integrated circuit device according to claim 12, wherein said first output MISFET and said second MISFET are n-channel MISFETs.
References Cited (Backward Citations)
US4893168A
Cited
US4609931A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-09 | 2000-01-08 | 2000-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-09 | 2004-01-08 | 2004-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-09 | 2008-01-08 | 2008-07-09 | $7700.00 | Window Closed / Lapsed |