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US5534713A
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Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers
Assignee: GlobalFoundries Inc
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Filing: 1994-05-20
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Granted: 1996-07-09
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Expires: 2014-05-20
Abstract
Abstract A method and a layered planar heterostructure comprising one of or both n and p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate wherein one layer is silicon or silicon germanium under tensile strain and one layer is silicon germanium under compressive strain whereby n channel field effect transistors may be formed with a silicon or silicon germanium layer under tension and p-channel field effect transistors may be formed with a silicon germanium layer under compression. The plurality of layers may be common to both subsequently formed p and n-channel field effect transistors which may be interconnected to form CMOS circuits. The invention overcomes the problem of forming separate and different layered structures for p and n-channel field effect transistors for CMOS circuitry on ULSI chips.
Inventors
- 👤 Khaled E. Ismail
- 👤 Frank Stern
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 03:52
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D84/00; H10D84/01; H10D84/02; H10D84/80; H10D84/82; H10D84/83; H10D84/85
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
194 words
A layered structure for forming both n and p channel field effect transistors therein comprising: a single crystalline substrate, a first layer of relaxed Si 1-x Ge x formed epitaxially on said substrate where the Ge fraction x is in the range from 0.20 to 0.5, a second layer of n doped Si 1-x Ge x formed epitaxially on said first layer, a third layer of undoped Si 1-x Ge x formed epitaxially on said second layer, a fourth layer selected from the group consisting of silicon and silicon-germanium formed epitaxially on said third layer whereby said fourth layer is under tensile strain, a fifth layer of relaxed Si 1-x Ge x formed epitaxially on said fourth layer, a sixth layer of Si 1-y Ge y formed epitaxially on said fifth layer where the Ge fraction y is in the range from 0.5 to 1.0 and where y-x>0.2 whereby said sixth layer is under compressive strain, a seventh layer of relaxed Si 1-x Ge x formed epitaxially on said sixth layer, an eighth layer of silicon formed epitaxially on said seventh layer, and a ninth layer of dielectric material formed over said eighth layer.
Claim 2
Dependent Claim
194 words
A layered structure for forming both n and p channel field effect transistors therein comprising: a single crystalline substrate, a first layer of relaxed Si 1-x Ge x formed epitaxially on said substrate where the Ge fraction x is in the range from 0.20 to 0.5, a second layer of n doped Si 1-x Ge x formed epitaxially on said first layer, a third layer of undoped Si 1-x Ge x formed epitaxially on said second layer, a fourth layer selected from the group consisting of silicon and silicon-germanium formed epitaxially on said third layer whereby said fourth layer is under tensile strain, a fifth layer of relaxed Si 1-x Ge x formed epitaxially on said fourth layer, a sixth layer of Si 1-y Ge y formed epitaxially on said fifth layer where the Ge fraction y is in the range from 0.5 to 1.0 and where y-x>0.2 whereby said sixth layer is under compressive strain, a seventh layer of relaxed Si 1-x Ge x formed epitaxially on said sixth layer, an eighth layer of silicon formed epitaxially on said seventh layer, and a ninth layer of dielectric material formed over said eighth layer.
Claim 3
Dependent Claim
28 words
The layered structure of claim 1 further including a tenth layer of polysilicon formed over said ninth layer of dielectric material and patterned lithographically to form gate electrodes.
Claim 4
Dependent Claim
37 words
The layered structure of claim 2 further including p regions passing from said sixth layer through said eighth layer on either side of at least one of said gate electrodes to form a p-channel field effect transistor.
Claim 5
Dependent Claim
20 words
The layered structure of claim 2 further including P-type source and drain regions located at least in said sixth layer.
Claim 6
Dependent Claim
37 words
The layered structure of claim 2 further including n regions passing from said fourth layer through said eighth layer on either side of at least one of said gate electrodes to form an n-channel field effect transistor.
Claim 7
Dependent Claim
20 words
The layered structure of claim 2 further including n-type source and drain regions located at least in said fourth layer.
Claim 8
Dependent Claim
37 words
The layered structure of claim 3 further including n regions passing from said fourth layer through said eighth layer on either side of at least one of said gate electrodes to form an n-channel field effect transistor.
Claim 9
Dependent Claim
29 words
The layered structure of claim 7 further including means for interconnecting said gate electrodes, said p regions and said n regions to form complementary metal oxide semiconductor (CMOS) logic.
Claim 10
Dependent Claim
32 words
The layered structure of claim 5 wherein said first layer further includes p type regions below the area of n channel transistors to prevent parasitic currents in or below said first layer.
Claim 11
Dependent Claim
32 words
The layered structure of claim 3 wherein said first layer further includes n type regions below the area of p channel transistors to prevent parasitic currents in or below said first layer.
Claim 12
Dependent Claim
28 words
The layered structure of claim 1 further including a tenth layer of metal formed over said ninth layer of dielectric material and patterned lithographically to form gate electrodes.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-09 | 2000-01-08 | 2000-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-09 | 2004-01-08 | 2004-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-09 | 2008-01-08 | 2008-07-09 | $7700.00 | Window Closed / Lapsed |