Method of multilevel dram sense and restore

Claim 1

A method of processing a data bit having one of four voltage levels stored in a dynamic random access memory (DRAM) cell capacitor comprising: (a) sensing whether or not the data bit voltage is above or below a voltage level midway between a highest and a lowest level of said four levels, and indicating a sign bit based thereon, (b) setting a threshold level based on the ratio of the capacitance of a storage cell capacitor to the total capacitance of three cell capacitors and three sub-bitlines and the value of a sign bit, and (c) sensing whether the data bit voltage is higher or lower than the threshold level, and indicating a magnitude bit based thereon, whereby the combination of the sign and magnitude bits represent which of the four levels is the voltage level data bit.

Claim 2

A method of processing a data bit having one of four voltage levels stored in a dynamic random access memory (DRAM) cell capacitor comprising: (a) sensing whether or not the data bit voltage is above or below a voltage level midway between a highest and a lowest level of said four levels, and indicating a sign bit based thereon, (b) setting a threshold level based on the ratio of the capacitance of a storage cell capacitor to the total capacitance of three cell capacitors and three sub-bitlines and the value of a sign bit, and (c) sensing whether the data bit voltage is higher or lower than the threshold level, and indicating a magnitude bit based thereon, whereby the combination of the sign and magnitude bits represent which of the four levels is the voltage level data bit.

Claim 5

A method of processing a data bit having one of plural charge levels stored in a DRAM cell capacitor comprising: (a) splitting a folded bitline into pairs of sub-bitlines each being comprised of a pair of conductors, to form one conductor pair BL and BL* and a second conductor pair BR and BR*, (b) precharging each of the conductors and a dummy cell capacitor to a precharge voltage, (c) connecting said cell capacitor to one of the conductors BL* of one of the bitline pairs, (d) connecting said conductor BL* to said conductor BR*, whereby charge stored on the cell capacitor is shared with both conductors and the dummy capacitor, (e) disconnecting the conductors BL* and BR* from each other and sensing the second conductor pair BR and BR*, whereby full logic level voltage is applied across the BR and BR* conductors with a polarity depending on whether a voltage resulting from the shared charge is higher or lower than the precharge voltage, the polarity designating a sign bit, (f) storing the full logic level voltage as determined by the sign bit from the BR* conductor, on the dummy capacitor, (g) connecting all of the conductors BL, BR and BR* together and precharging them while maintaining said full logic level voltage designating a sign bit on the dummy capacitor, (h) connecting the dummy capacitor to the connected BL, BR and BR* conductors, thus raising or lowering the voltage thereon above or below the precharge voltage, to provide a reference level r i , (i) disconnecting the conductor BL from the conductor pair BR and BR*, (j) sensing the one conductor pair BL and BL* to determine whether a voltage from the cell capacitor on the BL* conductor is higher or lower than the reference voltage level ri on the BL conductor, and applying full logic level, M, M across the conductors BL and BL* with a polarity depending on which of the conductors BL or BL* carries a higher voltage than the other, the polarity designating a magnitude bit, whereby the sign and magnitude bits are indicative of one of four logic states corresponding to one of said plural levels stored in the DRAM cell capacitor.

Claim 6

A method of processing a data bit having one of plural charge levels stored in a DRAM cell capacitor comprising: (a) splitting a folded bitline into pairs of sub-bitlines each being comprised of a pair of conductors, to form one conductor pair BL and BL* and a second conductor pair BR and BR*, (b) precharging each of the conductors and a dummy cell capacitor to a precharge voltage, (c) connecting said cell capacitor to one of the conductors BL* of one of the bitline pairs, (d) connecting said conductor BL* to said conductor BR*, whereby charge stored on the cell capacitor is shared with both conductors and the dummy capacitor, (e) disconnecting the conductors BL* and BR* from each other and sensing the second conductor pair BR and BR*, whereby full logic level voltage is applied across the BR and BR* conductors with a polarity depending on whether a voltage resulting from the shared charge is higher or lower than the precharge voltage, the polarity designating a sign bit, (f) storing the full logic level voltage as determined by the sign bit from the BR* conductor, on the dummy capacitor, (g) connecting all of the conductors BL, BR and BR* together and precharging them while maintaining said full logic level voltage designating a sign bit on the dummy capacitor, (h) connecting the dummy capacitor to the connected BL, BR and BR* conductors, thus raising or lowering the voltage thereon above or below the precharge voltage, to provide a reference level r i , (i) disconnecting the conductor BL from the conductor pair BR and BR*, (j) sensing the one conductor pair BL and BL* to determine whether a voltage from the cell capacitor on the BL* conductor is higher or lower than the reference voltage level ri on the BL conductor, and applying full logic level, M, M across the conductors BL and BL* with a polarity depending on which of the conductors BL or BL* carries a higher voltage than the other, the polarity designating a magnitude bit, whereby the sign and magnitude bits are indicative of one of four logic states corresponding to one of said plural levels stored in the DRAM cell capacitor.

Claim 8

A method of processing two bits of binary data in a DRAM in which each bitline is divided into two subbitlines comprising: (a) charging two sub-bitlines to a full logic level representing one of the bits, (b) charging one other sub-bitline to a full logic level representing the other bit, (c) charge sharing the three sub-bitlines to one of four voltage levels and storing a result in a memory cell on one subbitline whereby two bits of data are stored in a single DRAM cell.

Claim 9

A method of processing two bits of binary data in a DRAM in which each bitline is divided into two subbitlines comprising: (a) charging two sub-bitlines to a full logic level representing one of the bits, (b) charging one other sub-bitline to a full logic level representing the other bit, (c) charge sharing the three sub-bitlines to one of four voltage levels and storing a result in a memory cell on one subbitline whereby two bits of data are stored in a single DRAM cell.

Claim 10

A method of restoring a DRAM charge storage cell on one of two bitlines, each bitline divided into two subbitlines, by charge sharing two sub-bitlines with a sign bit and a single sub-bitline with a magnitude bit, to obtain reference levels against which a cell voltage magnitude is sensed, wherein the sign bit S and magnitude bit M define reference levels in accordance with the truth table: ______________________________________ S M 2S+M ______________________________________ 1 1 (2Vdd+Vdd)/3 = Vdd 1 0 (2Vdd+0)/3 = 2Vdd/3 0 1 (0+Vdd)/3 = Vdd/3 0 0 (0+0)/3 = 0 ______________________________________

Claim 11

A method of restoring a DRAM charge storage cell on one of two bitlines, each bitline divided into two subbitlines, by charge sharing two sub-bitlines with a sign bit and a single sub-bitline with a magnitude bit, to obtain reference levels against which a cell voltage magnitude is sensed, wherein the sign bit S and magnitude bit M define reference levels in accordance with the truth table: ______________________________________ S M 2S+M ______________________________________ 1 1 (2Vdd+Vdd)/3 = Vdd 1 0 (2Vdd+0)/3 = 2Vdd/3 0 1 (0+Vdd)/3 = Vdd/3 0 0 (0+0)/3 = 0 ______________________________________

Claim 12

A method of processing a data bit having one of plural charge levels stored in a DRAM storage cell capacitor comprising: (a) splitting a folded bitline into pairs of sub-bitlines each being comprised of a pair of conductors, to form one conductor pair and a second conductor pair, (b) precharging each of the conductors and a dummy cell capacitor to a precharge voltage, (c) connecting said storage cell capacitor to one of the conductors of one of the bitline pairs with the dummy cell capacitor disconnected therefrom, (d) connecting said conductor connected to the cell capacitor to another conductor, whereby charge stored on the storage cell capacitor is shared with both conductors and a dummy cell capacitor, (e) disconnecting the conductors of step (d) from each other and sensing one of the conductors of step (d), whereby full logic level voltage is applied across a pair of conductors with a polarity depending on whether a voltage resulting from the shared charge is higher or lower than the precharge voltage, the polarity designating a sign bit, (f) storing the full logic level voltage as determined by the sign bit on a cell capacitor, (g) precharging three conductors while maintaining said full logic level voltage designating a sign bit on the cell capacitor of step (f), (h) connecting the cell capacitor of step (f) to the three precharged conductors with cell capacitors, thus raising or lowering the voltage thereon above or below the precharge voltage, to provide a reference level r i , (i) disconnecting one of the three conductors, (j) sensing said one of the three conductors of step (i) to determine whether a voltage from the storage cell capacitor on another conductor is higher or lower than the reference voltage level on said one of the three conductors, and applying full logic level across the conductors with a polarity depending on which of the conductors carries a higher voltage than the other, the polarity designating a magnitude bit, wherein the sign and magnitude bits are indicative of one of four logic states corresponding to one of said plural levels stored in the DRAM cell capacitor.

Claim 13

A method of processing a data bit having one of plural charge levels stored in a DRAM storage cell capacitor comprising: (a) splitting a folded bitline into pairs of sub-bitlines each being comprised of a pair of conductors, to form one conductor pair and a second conductor pair, (b) precharging each of the conductors and a dummy cell capacitor to a precharge voltage, (c) connecting said storage cell capacitor to one of the conductors of one of the bitline pairs with the dummy cell capacitor disconnected therefrom, (d) connecting said conductor connected to the cell capacitor to another conductor, whereby charge stored on the storage cell capacitor is shared with both conductors and a dummy cell capacitor, (e) disconnecting the conductors of step (d) from each other and sensing one of the conductors of step (d), whereby full logic level voltage is applied across a pair of conductors with a polarity depending on whether a voltage resulting from the shared charge is higher or lower than the precharge voltage, the polarity designating a sign bit, (f) storing the full logic level voltage as determined by the sign bit on a cell capacitor, (g) precharging three conductors while maintaining said full logic level voltage designating a sign bit on the cell capacitor of step (f), (h) connecting the cell capacitor of step (f) to the three precharged conductors with cell capacitors, thus raising or lowering the voltage thereon above or below the precharge voltage, to provide a reference level r i , (i) disconnecting one of the three conductors, (j) sensing said one of the three conductors of step (i) to determine whether a voltage from the storage cell capacitor on another conductor is higher or lower than the reference voltage level on said one of the three conductors, and applying full logic level across the conductors with a polarity depending on which of the conductors carries a higher voltage than the other, the polarity designating a magnitude bit, wherein the sign and magnitude bits are indicative of one of four logic states corresponding to one of said plural levels stored in the DRAM cell capacitor.