Source-switched charge pump circuit

Claim 2

A charge pump circuit comprising: a charging transistor having a gate coupled to receive a first biasing voltage, the charging transistor being a p-channel field effect transistor (FET); a discharging transistor having a gate coupled to receive a second biasing voltage, wherein a drain of the discharging transistor is coupled to a drain of the charging transistor, the discharging transistor being an n-channel FET wherein the charging transistor and the discharging transistor are matched devices; a first complementary switch coupled in series between a source of the charging transistor and a first supply voltage, the first complementary switch being switched on and off in response to a first pair of complementary signals; a second complementary switch coupled in series between a source of the discharging transistor and a second supply voltage, the second complementary switch being switched on and off in response to a second pair of complementary signals; a biasing circuit, providing the first and second biasing voltages, comprising: a current source outputting a reference current; a current mirror circuit coupled to the current source and the charging and discharging transistors such that the reference current is mirrored to the charging and discharging transistors; the current mirror circuit comprising: a first field effect transistor (FET), having matched characteristics to the charging transistor, having a source, a drain, and a gate, wherein the drain of the first FET is coupled to the gate of the first FET, the current source being coupled between the drain of the first FET and the second supply voltage; a first impedance coupled between the first supply voltage and the source of the first FET, the first impedance being a complementary switch that matches the characteristics of the first complementary switch and being equivalent to a first switch impedance of the first complementary switch when the first complementary switch is switched on; a second FET, having matched characteristics to the charging transistor, having a source, a drain, and a gate, wherein the gate of the second FET are coupled to the gate of the first FET and a gate of the charging transistor; a second impedance coupled between the first supply voltage and the source of the second FET, the second impedance being a complementary switch that matches the characteristics of the first complementary switch and being equivalent to the first switch impedance of the first complementary switch when the first complementary switch is switched on; a third FET having matched characteristics to the discharging transistor, having a source, a drain, and a gate, wherein the drain of the third FET is coupled to the gate of the third FET, a gate of the discharging transistor, and the drain of the second FET; and a third impedance coupled between the second supply voltage and the source of the third FET, the third impedance being a complementary switch that matches the characteristics of the second complementary switch and being equivalent to a second switch impedance of the second complementary switch when the second complementary switch is switched on.

Claim 3

A phase-locked loop (PLL) comprising: a loop filter; a voltage controlled oscillator (VCO) having an input coupled to the loop filter, the VCO outputting a first signal in response to a voltage of the loop filter; a phase detector circuit coupled to the first signal and a reference signal; a charge pump circuit coupled to the phase detector circuit and the loop filter, the charge pump circuit setting the voltage of the loop filter in response to an output of the phase detector, the charge pump circuit comprising: a charging transistor having a gate coupled to receive a first biasing voltage, the charging transistor being a p-channel field effect transistor (FET); a discharging transistor having a gate coupled to receive a second biasing voltage, wherein a drain of the discharging transistor is coupled to a drain of the charging transistor, the discharging transistor being an n-channel FET, wherein the charging and discharging transistors are matched devices; a first complementary switch coupled in series between a source of the charging transistor and a first supply voltage, the first complementary switch being switched on and off in response to a first pair of complementary signals; a second complementary switch coupled in series between a source of the discharging transistor and a second supply voltage, the second complementary switch being switched on and off in response to a second pair of complementary signals; a biasing circuit, providing the first and second biasing voltages, comprising a current source outputting a reference current and a current mirror circuit coupled to the current source and the charging and discharging transistors such that the reference current is mirrored to the charging and discharging transistors; the current mirror circuit comprising: a first field effect transistor (FET), having matched characteristics to the charging transistor, having a source, a drain, and a gate, wherein the drain of the first FET is coupled to the gate of the first FET, the current source being coupled between the drain of the first field effect transistor and the second supply voltage; a first impedance coupled between the first supply voltage and the source of the first FET, the first impedance being a complementary switch that matches the characteristics of the first complementary switch and being equivalent to a first switch impedance of the first complementary switch when the first complementary switch is switched on; a second FET, having matched characteristics to the charging transistor, having a source, a drain, and a gate, wherein the gate of the second FET are coupled to the gate of the first FET and a gate of the charging transistor; a second impedance coupled between the first supply voltage and the source of the second FET, the second impedance being a complementary switch that matches the characteristics of the first complementary switch and being equivalent to the first switch impedance of the first complementary switch when the first complementary switch is switched on; a third FET, having matched characteristics to the discharging transistor, having a source, a drain, and a gate, wherein the drain of the third FET is coupled to the gate of the third FET, a gate of the discharging transistor, and the drain of the second FET; and a third impedance coupled between the second supply voltage and the source of the third FET, the third impedance being a complementary switch that matches the characteristics of the second complementary switch and being equivalent to a second switch impedance of the second complementary switch when the second complementary switch is switched on.

Claim 4

A phase-locked loop (PLL) comprising: a loop filter; a voltage controlled oscillator (VCO) having an input coupled to the loop filter, the VCO outputting a first signal in response to a voltage of the loop filter; a phase detector circuit coupled to the first signal and a reference signal; a charge pump circuit coupled to the phase detector circuit and the loop filter, the charge pump circuit setting the voltage of the loop filter in response to an output of the phase detector, the charge pump circuit comprising: a charging transistor having a gate coupled to receive a first biasing voltage, the charging transistor being a p-channel field effect transistor (FET); a discharging transistor having a gate coupled to receive a second biasing voltage, wherein a drain of the discharging transistor is coupled to a drain of the charging transistor, the discharging transistor being an n-channel FET, wherein the charging and discharging transistors are matched devices; a first complementary switch coupled in series between a source of the charging transistor and a first supply voltage, the first complementary switch being switched on and off in response to a first pair of complementary signals; a second complementary switch coupled in series between a source of the discharging transistor and a second supply voltage, the second complementary switch being switched on and off in response to a second pair of complementary signals; a biasing circuit, providing the first and second biasing voltages, comprising a current source outputting a reference current and a current mirror circuit coupled to the current source and the charging and discharging transistors such that the reference current is mirrored to the charging and discharging transistors; the current mirror circuit comprising: a first field effect transistor (FET), having matched characteristics to the charging transistor, having a source, a drain, and a gate, wherein the drain of the first FET is coupled to the gate of the first FET, the current source being coupled between the drain of the first field effect transistor and the second supply voltage; a first impedance coupled between the first supply voltage and the source of the first FET, the first impedance being a complementary switch that matches the characteristics of the first complementary switch and being equivalent to a first switch impedance of the first complementary switch when the first complementary switch is switched on; a second FET, having matched characteristics to the charging transistor, having a source, a drain, and a gate, wherein the gate of the second FET are coupled to the gate of the first FET and a gate of the charging transistor; a second impedance coupled between the first supply voltage and the source of the second FET, the second impedance being a complementary switch that matches the characteristics of the first complementary switch and being equivalent to the first switch impedance of the first complementary switch when the first complementary switch is switched on; a third FET, having matched characteristics to the discharging transistor, having a source, a drain, and a gate, wherein the drain of the third FET is coupled to the gate of the third FET, a gate of the discharging transistor, and the drain of the second FET; and a third impedance coupled between the second supply voltage and the source of the third FET, the third impedance being a complementary switch that matches the characteristics of the second complementary switch and being equivalent to a second switch impedance of the second complementary switch when the second complementary switch is switched on.