Patent US5530933A successfully refreshed from Google Patents.
US5530933A
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Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus
Assignee: Hewlett Packard Development Co LP
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Filing: 1994-02-24
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Granted: 1996-06-25
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Expires: 2014-02-24
Abstract
Abstract A coherency scheme of use with a system having a bus, a main memory, a main memory controller for accessing main memory in response to transactions received on the bus, and a set of processor modules coupled to the bus. Each processor module has a cache memory and is capable of transmitting coherent transactions on the bus to other processor modules and to the main memory controller. Each processor module detects coherent transactions issued on the bus and performs cache coherency checks for each of the coherent transactions. Each processor module has a coherency queue for storing all transactions issued on the bus and for performing coherency checks for the transactions in first-in, first-out order. When a module transmits a coherent transaction on a bus, it places its own transaction into its own coherency queue.
Inventors
- 👤 Craig R. Frink
- 👤 William R. Bryg
- 👤 Kenneth K. Chan
- 👤 Thomas R. Hotchkiss
- 👤 Robert D. Odineal
- 👤 James B. Williams
- 👤 Michael L. Ziegler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:02
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
217 words
A data processing system comprising: a bus for transmitting and receiving information specifying transactions to be carried out by processing modules coupled to said bus; a memory controller coupled to said bus for servicing transactions transmitted on said bus, said transactions being issued one at a time on said bus thereby defining an order for said transactions, said transactions comprising transactions requiring coherency checks prior to said memory controller servicing said transactions by causing data normally stored in a central memory connected to said memory controller to be placed on said bus, said data being identified by a memory address specifying a location in said central memory at which said data is stored; and a plurality of processing modules coupled to said bus, each of said processing modules comprising a coherency check means for performing a coherency check on data stored in a memory associated with that processing module and for reporting a result from said coherency check to said memory controller; wherein each of said coherency checks corresponds to a transaction issued on said bus, wherein said coherency checks are performed in said order of the transactions being issued on the bus, and wherein said memory controller waits until each of said coherency check means has reported before servicing one of said transactions requiring coherency checks.
Claim 2
Dependent Claim
217 words
A data processing system comprising: a bus for transmitting and receiving information specifying transactions to be carried out by processing modules coupled to said bus; a memory controller coupled to said bus for servicing transactions transmitted on said bus, said transactions being issued one at a time on said bus thereby defining an order for said transactions, said transactions comprising transactions requiring coherency checks prior to said memory controller servicing said transactions by causing data normally stored in a central memory connected to said memory controller to be placed on said bus, said data being identified by a memory address specifying a location in said central memory at which said data is stored; and a plurality of processing modules coupled to said bus, each of said processing modules comprising a coherency check means for performing a coherency check on data stored in a memory associated with that processing module and for reporting a result from said coherency check to said memory controller; wherein each of said coherency checks corresponds to a transaction issued on said bus, wherein said coherency checks are performed in said order of the transactions being issued on the bus, and wherein said memory controller waits until each of said coherency check means has reported before servicing one of said transactions requiring coherency checks.
Claim 3
Dependent Claim
35 words
The data processing system of claim 1, wherein each of said processing modules comprises a queue for storing information specifying coherency checks to be performed by said coherency check means included in that processing module.
Claim 4
Dependent Claim
41 words
The data processing system of claim 1 wherein each said processing module comprises means for detecting transactions on said bus requiring coherency checking and for initiating a coherency check in response to detecting one of said transactions requiring a coherency check.
Claim 5
Dependent Claim
68 words
The data processing system of claim 1, wherein said transactions serviced by said main memory controller comprise a read transaction that requests data from a specified memory address in said central memory and a write transaction that sends data to said specified memory address in said central memory, and wherein said main memory controller comprises means for causing said write transaction to be performed before said read transaction.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-25 | 1999-12-25 | 2000-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-25 | 2003-12-25 | 2004-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-25 | 2007-12-25 | 2008-06-25 | $7700.00 | Window Closed / Lapsed |