Multi-processor computer systems having shared memory and private cache memories

Claim 2

In a computer system having a main memory for storing a set of data, said computer system further having a plurality of processors, each processor having an associated cache memory for storing a subset of the data stored in said main memory, said computer system further having a system bus for intercoupling the processors and the main memory and for intercoupling each of the processors with any other of the processors, an apparatus for maintaining the integrity of data stored in the main memory and in the cache memories comprising: a. a read data queue for each processor, said read data queue coupled to said system bus, said invalidate queue having a plurality of entries, each entry having a data field for storing read data to be processed into said processor's cache memory and a valid bit field for identifying a full read data entry; and b. an invalidate queue for each processor, said invalidate queue having a plurality of entries, each entry having an address field for storing invalidates, a valid bit field for identifying a full invalidate entry and a flush bit field for indicating an invalidate to be processed, wherein upon initiation of a read request by any of said processors for data for which the memory address of that data is not resident in the cache corresponding to said processor, said processor directs that the valid bit field for each entry in its associated invalidate queue be read to it associated flush bit field and commences processing all invalidates for which a flush bit is set while halting the processing of read data values in the read data queue until all said invalidates have been processed.

Claim 3

In a computer system having a main memory and further having a plurality of processors, each of said processors having an associated cache memory, and each of said processors further having a read data queue, said read data queue having a plurality of entries, each of said entries having a data field for holding a read data value to be processed to the processor's associated cache memory and a valid bit field for indicating a full read data value, each of said processors further having an invalidate queue, said invalidate queue having a plurality of entries, each of said entries having an address field for holding an invalidate value to be processed to the processor's associated cache memory, a valid bit field for indicating a full invalidate value and a flush bit field for indicating an invalidate value which is to be processed before the next read data value is to be processed, a method of maintaining the coherency of the data in the main memory and the cache memories comprising: a. issuing a read transaction from one of said processors for which the memory address of the requested data is not resident in the cache of said processor; b. copying each valid bit in the invalidate queue to its associated flush bit to set selected flush bits; c. commencing the processing of all invalidates in the invalidate queue for which its associated flush bit is set; d. issuing a read data transaction from the main memory of the system to the read data queue of the processor issuing the read transaction; e. pausing the processing of the contents in the read data queue to its corresponding cache memory until all of the invalidates having flush bits set have been processed; and f. continuing to process the contents in the read data queue to its corresponding cache memory.

Claim 4

In a computer system having a main memory and further having a plurality of processors, each of said processors having an associated cache memory, and each of said processors further having a read data queue, said read data queue having a plurality of entries, each of said entries having a data field for holding a read data value to be processed to the processor's associated cache memory and a valid bit field for indicating a full read data value, each of said processors further having an invalidate queue, said invalidate queue having a plurality of entries, each of said entries having an address field for holding an invalidate value to be processed to the processor's associated cache memory, a valid bit field for indicating a full invalidate value and a flush bit field for indicating an invalidate value which is to be processed before the next read data value is to be processed, a method of maintaining the coherency of the data in the main memory and the cache memories comprising: a. issuing a read transaction from one of said processors for which the memory address of the requested data is not resident in the cache of said processor; b. copying each valid bit in the invalidate queue to its associated flush bit to set selected flush bits; c. commencing the processing of all invalidates in the invalidate queue for which its associated flush bit is set; d. issuing a read data transaction from the main memory of the system to the read data queue of the processor issuing the read transaction; e. pausing the processing of the contents in the read data queue to its corresponding cache memory until all of the invalidates having flush bits set have been processed; and f. continuing to process the contents in the read data queue to its corresponding cache memory.

Claim 5

A computer system, comprising: a. accessible main memory for storing a set of data; b. a plurality of processors for processing data, each of said processors having associated therewith a secondary memory for storing a subset of the data stored in said main memory, said processors further comprising means for issuing read requests to read data from said memory; c. a system bus for connecting main memory and each of said processors and for connecting each of said processors to any other of said processors; d. buffer storage means associated with each of said processors for storing data read from said main memory to be processed to said secondary memory; e. invalidate means associated with each of said processors and requiring processing by said processors to said secondary memory, said invalidate means for storing valid addresses of data in said secondary memory that are invalid; and f. serialization means for causing, upon the issuance of a read request, that all valid addresses in said invalidate means at the time of the issuance of the read request are processed before any data stored in said buffer storage means are processed to said secondary memory.

Claim 6

A computer system, comprising: a. accessible main memory for storing a set of data; b. a plurality of processors for processing data, each of said processors having associated therewith a secondary memory for storing a subset of the data stored in said main memory, said processors further comprising means for issuing read requests to read data from said memory; c. a system bus for connecting main memory and each of said processors and for connecting each of said processors to any other of said processors; d. buffer storage means associated with each of said processors for storing data read from said main memory to be processed to said secondary memory; e. invalidate means associated with each of said processors and requiring processing by said processors to said secondary memory, said invalidate means for storing valid addresses of data in said secondary memory that are invalid; and f. serialization means for causing, upon the issuance of a read request, that all valid addresses in said invalidate means at the time of the issuance of the read request are processed before any data stored in said buffer storage means are processed to said secondary memory.

Claim 7

A computer system, comprising: a main memory for storing a set of data; a plurality of processors for processing data, each of said processors having associated therewith a secondary memory for storing a subset of the data stored in said main memory, each of said processors further including means for issuing read requests to read data from said main memory; a system bus for interconnecting said main memory and each of said processors; each of said processors having invalidate means for storing addresses of data in said secondary memory that are invalid; and serialization means activated, after the issuance of one of said read requests, to process all addresses which are in said invalidate means at the time of said issuance of the read request before any data in response to said read request are loaded to said secondary memory.

Claim 8

A computer system, comprising: a main memory for storing a set of data; a plurality of processors for processing data, each of said processors having associated therewith a secondary memory for storing a subset of the data stored in said main memory, each of said processors further including means for issuing read requests to read data from said main memory; a system bus for interconnecting said main memory and each of said processors; each of said processors having invalidate means for storing addresses of data in said secondary memory that are invalid; and serialization means activated, after the issuance of one of said read requests, to process all addresses which are in said invalidate means at the time of said issuance of the read request before any data in response to said read request are loaded to said secondary memory.

Claim 9

A system according to claim 4 wherein each of said processors has buffer storage means in a path between said system bus and said secondary memory, said buffer storage means storing data read from said memory in response to said read requests before said data is loaded to said secondary memory.

Claim 10

A system according to claim 4 wherein said invalidate means in each processor includes a FIFO memory containing a plurality of memory locations and each one of the memory locations has a field for one of said addresses of data that are invalid and a field for a flush bit, and said serialization means operates in response to said flush bits.

Claim 11

A system according to claim 6 wherein said invalidate means in each processor includes logic means responsive to all of said flush bits to control said serialization means.

Claim 14

A method according to claim 8 including the step of activating an indicator for each of said temporarily stored addresses existing when a read request is initiated.

Claim 15

A method according to claim 9 including the step of detecting whether any of said indicators are activated before said step of moving data to said cache.

Claim 16

A method according to claim 10 including the step of setting a valid bit for each of said temporarily stored addresses to indicate that an address is stored in a location.

Claim 17

A method according to claim 11 wherein said step of checking includes activating said indicators based upon said valid bits.

Claim 18

A computer system comprising a plurality of processors sharing a main memory via a common system bus, each of said processors having a cache, each of processors making read requests and write requests to said main memory via said system bus, each of said processors including: means for temporarily storing addresses of write requests made to main memory, a buffer for storing data received from main memory in response to a read request by the processor, and means for checking said addresses of write requests occurring before a given read request made by the processor before loading said data from said buffer to said cache.

Claim 19

A computer system comprising a plurality of processors sharing a main memory via a common system bus, each of said processors having a cache, each of processors making read requests and write requests to said main memory via said system bus, each of said processors including: means for temporarily storing addresses of write requests made to main memory, a buffer for storing data received from main memory in response to a read request by the processor, and means for checking said addresses of write requests occurring before a given read request made by the processor before loading said data from said buffer to said cache.

Claim 20

A system according to claim 13 wherein said means for temporarily storing addresses includes means for setting an indicator bit for each stored address existing when a read request is made.

Claim 21

A system according to claim 14 wherein said means for checking includes means for detecting whether or not any of said indicator bits are set.

Claim 22

A system according to claim 15 wherein said means for temporarily storing addresses includes means for setting a valid bit for each location into which a write address is stored.

Claim 23

A system according to claim 16 wherein said means for checking includes means for loading all of said valid bits to said indicator bits.