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US5530668A
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US
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Ferroelectric memory sensing scheme using bit lines precharged to a logic one voltage
Assignee: Cypress Semiconductor Corp
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Filing: 1995-04-12
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Granted: 1996-06-25
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Expires: 2015-04-12
Abstract
Abstract In a ferroelectric memory cell having a plate line, a word line and a bit line coupled to a sense amplifier, a sensing method includes the steps of precharging the bit line to a logic one voltage, setting the word and plate lines to an initial logic zero voltage, stepping the word line from the initial logic zero voltage to the logic one voltage, stepping the plate line from the initial logic zero voltage to the logic one voltage, activating the sense amplifier to resolve voltage developed on the bit line to a full logic voltage while the word and plate lines are at the logic one voltage, and returning the word and plate lines to the initial logic zero voltage.
Inventors
- 👤 Wen-Foo Chern
- 👤 Dennis Wilson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:18
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/22
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
146 words
In a ferroelectric memory cell having a plate line, a word line, and a bit line, the bit line being coupled to a sense amplifier, a sensing method comprising the steps of: biasing all N-wells in the sense amplifier to a voltage greater than the most positive voltage excursion of the bit line; precharging the bit line to a logic one voltage; setting the word and plate lines to an initial logic zero voltage; stepping the word line from the initial logic zero voltage to the logic one voltage; stepping the plate line from the initial logic zero voltage to the logic one voltage; activating the sense amplifier to resolve voltage developed on the bit line to a full logic voltage while the word and plate lines are at the logic one voltage; and returning the word and plate lines to the initial logic zero voltage.
Claim 2
Dependent Claim
146 words
In a ferroelectric memory cell having a plate line, a word line, and a bit line, the bit line being coupled to a sense amplifier, a sensing method comprising the steps of: biasing all N-wells in the sense amplifier to a voltage greater than the most positive voltage excursion of the bit line; precharging the bit line to a logic one voltage; setting the word and plate lines to an initial logic zero voltage; stepping the word line from the initial logic zero voltage to the logic one voltage; stepping the plate line from the initial logic zero voltage to the logic one voltage; activating the sense amplifier to resolve voltage developed on the bit line to a full logic voltage while the word and plate lines are at the logic one voltage; and returning the word and plate lines to the initial logic zero voltage.
Claim 3
Dependent Claim
53 words
The method of claim 1 in which the step of stepping the word line voltage from the initial logic zero voltage to the logic one voltage comprises the step of stepping the word line voltage from the initial logic zero voltage to a bootstrapped logic one voltage greater than the logic one voltage.
Claim 4
Dependent Claim
23 words
The method of claim 1 further comprising the step of coupling the bit line to a sense amplifier comprised solely of N-channel transistors.
Claim 5
Dependent Claim
145 words
In a ferroelectric memory cell having a plate line, a word line, and a bit line, the bit line being coupled to a sense amplifier, a sensing method comprising the steps of: biasing all N-wells in the sense amplifier to a voltage greater than the most positive voltage excursion of the bit line; precharging the bit line to a logic one voltage; setting the word and plate lines to an initial logic zero voltage; stepping the word line from the initial logic zero voltage to the logic one voltage; activating the sense amplifier to resolve voltage developed on the bit line to a full logic voltage while the word line is at the logic one voltage and the plate line is at the logic zero voltage; pulsing the plate line with a positive-going pulse; and returning the word line to the initial logic zero voltage.
Claim 6
Dependent Claim
145 words
In a ferroelectric memory cell having a plate line, a word line, and a bit line, the bit line being coupled to a sense amplifier, a sensing method comprising the steps of: biasing all N-wells in the sense amplifier to a voltage greater than the most positive voltage excursion of the bit line; precharging the bit line to a logic one voltage; setting the word and plate lines to an initial logic zero voltage; stepping the word line from the initial logic zero voltage to the logic one voltage; activating the sense amplifier to resolve voltage developed on the bit line to a full logic voltage while the word line is at the logic one voltage and the plate line is at the logic zero voltage; pulsing the plate line with a positive-going pulse; and returning the word line to the initial logic zero voltage.
Claim 7
Dependent Claim
53 words
The method of claim 4 in which the step of stepping the word line voltage from the initial logic zero voltage to the logic one voltage comprises the step of stepping the word line voltage from the initial logic zero voltage to a bootstrapped logic one voltage greater than the logic one voltage.
Claim 8
Independent Claim
22 words
The method of claim 4further comprising the step of coupling the bit line to a sense amplifier comprised solely of N-channel transistors.
Claim 9
Dependent Claim
134 words
In a ferroelectric memory cell having a plate line, a word line, and a bit line, the bit line being coupled to a sense amplifier, a sensing method comprising the steps of: precharging the bit line to a power supply voltage, the power supply voltage representing a logic one voltage; setting the word and plate lines to an initial logic zero voltage; stepping the word line from the initial logic zero voltage to the logic one voltage; stepping the plate line from the initial logic zero voltage to the logic one voltage; activating the sense amplifier to resolve voltage developed on the bit line to a full logic voltage while the word and plate lines are at the logic one voltage; and returning the word and plate lines to the initial logic zero voltage.
Claim 10
Dependent Claim
134 words
In a ferroelectric memory cell having a plate line, a word line, and a bit line, the bit line being coupled to a sense amplifier, a sensing method comprising the steps of: precharging the bit line to a power supply voltage, the power supply voltage representing a logic one voltage; setting the word and plate lines to an initial logic zero voltage; stepping the word line from the initial logic zero voltage to the logic one voltage; stepping the plate line from the initial logic zero voltage to the logic one voltage; activating the sense amplifier to resolve voltage developed on the bit line to a full logic voltage while the word and plate lines are at the logic one voltage; and returning the word and plate lines to the initial logic zero voltage.
Claim 11
Dependent Claim
26 words
The method of claim 7 in which the precharging step comprises the step of precharging the bit line to a power supply voltage of five volts.
Claim 12
Dependent Claim
26 words
The method of claim 7 in which the precharging step comprises the step of precharging the bit line to a power supply voltage of 3.3 volts.
Claim 13
Dependent Claim
53 words
The method of claim 7 in which the step of stepping the word line voltage from the initial logic zero voltage to the logic one voltage comprises the step of stepping the word line voltage from the initial logic zero voltage to a bootstrapped logic one voltage greater than the logic one voltage.
Claim 14
Dependent Claim
31 words
The method of claim 7 further comprising the step of biasing all N-wells in the sense amplifier to a voltage greater than the most positive voltage excursion of the bit line.
Claim 15
Dependent Claim
23 words
The method of claim 7 further comprising the step of coupling the bit line to a sense amplifier comprised solely of N-channel transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-25 | 1999-12-25 | 2000-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-25 | 2003-12-25 | 2004-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-25 | 2007-12-25 | 2008-06-25 | $7700.00 | Window Closed / Lapsed |