Patent US5530380A successfully refreshed from Google Patents.
US5530380A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Decoder circuit which resists a fluctuation of a power supply
Assignee: Renesas Electronics Corp
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Filing: 1994-12-06
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Granted: 1996-06-25
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Expires: 2014-12-06
Abstract
Abstract A decoder circuit includes p-channel MOS transistors P 1 and P 2 , n-channel MOS transistors N 1 to N 4 having gates to which data signals D 1 to D 4 are inputted, respectively, an n-channel MOS transistor N s connected in series to the n-channel MOS transistors N 1 to N 4 and having a gate to which the precharging signal Φ is inputted, and an n-channel MOS transistor N 5 connected between P 2 and N 1 . In the decoder circuit, the gate of N 5 is connected to the drain of P 2 , and a capacity C H is connected between the gate of N 5 and a power potential. In a holding state, the power potential is held by the aid of the capacity C H connected to the gate of N 5 .
Inventors
- 👤 Chiaki Kondoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 18:59
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/10; H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361; H03K19/01; H03K19/017; H03K19/01728; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0963
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
174 words
A transistor circuit, comprising: an output terminal; a first MOS transistor having a source connected to a first power supply, a gate receiving a precharging signal, and drain connected to said output terminal; a second MOS transistor having a source connected to a second power supply and a gate receiving said precharging signal, said first MOS transistor being of a type different from that of said second MOS transistor; a plurality of third MOS transistors of the same type as said second MOS transistor connected in series connected between a drain of said second MOS transistor and a circuit node, said third MOS transistors receiving at gates thereof data signals, respectively; a fourth MOS transistor of the same type as said second MOS transistor connected between said output terminal and said circuit node; and a fifth MOS transistor of the same type as said first MOS transistor having a source connected to said first power supply, a gate receiving said precharging signal and a drain connected to a gate of said fourth MOS transistor.
Claim 2
Dependent Claim
174 words
A transistor circuit, comprising: an output terminal; a first MOS transistor having a source connected to a first power supply, a gate receiving a precharging signal, and drain connected to said output terminal; a second MOS transistor having a source connected to a second power supply and a gate receiving said precharging signal, said first MOS transistor being of a type different from that of said second MOS transistor; a plurality of third MOS transistors of the same type as said second MOS transistor connected in series connected between a drain of said second MOS transistor and a circuit node, said third MOS transistors receiving at gates thereof data signals, respectively; a fourth MOS transistor of the same type as said second MOS transistor connected between said output terminal and said circuit node; and a fifth MOS transistor of the same type as said first MOS transistor having a source connected to said first power supply, a gate receiving said precharging signal and a drain connected to a gate of said fourth MOS transistor.
Claim 3
Dependent Claim
26 words
The transistor circuit as claimed in claim 1, further comprising a capacitor connected between the gate of said fourth MOS transistor and said second power supply.
Claim 4
Dependent Claim
93 words
A decoder circuit comprising an output node, first precharging means for precharging said output node to a first potential in response to a precharging signal, a transistor circuit having first and second nodes and at least one first transistor coupled between said first and second nodes and receiving at a gate thereof an input signal, a second transistor inserted between said output node and said first node of said transistor circuit, and second precharging means for precharging a gate of said second transistor to said first potential in response to said precharging signal.
Claim 5
Dependent Claim
93 words
A decoder circuit comprising an output node, first precharging means for precharging said output node to a first potential in response to a precharging signal, a transistor circuit having first and second nodes and at least one first transistor coupled between said first and second nodes and receiving at a gate thereof an input signal, a second transistor inserted between said output node and said first node of said transistor circuit, and second precharging means for precharging a gate of said second transistor to said first potential in response to said precharging signal.
Claim 6
Dependent Claim
30 words
The decoder circuit as claimed in claim 3, further comprising discharging means for discharging said second node of said transistor circuit to a second potential when said precharging signal disappears.
Claim 7
Dependent Claim
124 words
The decoder circuit as claimed in claim 4, wherein said first precharging means includes a third transistor connected between a first power supply line supplying said first potential and said output node and having a gate supplied with said precharging signal, said discharging means including a fourth transistor connected between a second power supply line supplying said second potential and said second node and having a gate supplied with said precharging signal, said second precharging means including a fifth transistor connected between said first power supply line and said gate of said second transistor and having a gate supplied with said precharging signal, said third and fifth transistor are of a first channel type, and said fourth transistor is of a second channel type.
References Cited (Backward Citations)
WO1982000741A1
Cited
US4345170A
Cited
WO1985004539A1
Cited
US4780626A
Cited
US4849658A
Cited
EP0283228A2
Cited
US4827160A
Cited
US4797580A
Cited
US5144163A
Cited
US5146115A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-25 | 1999-12-25 | 2000-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-25 | 2003-12-25 | 2004-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-25 | 2007-12-25 | 2008-06-25 | $7700.00 | Window Closed / Lapsed |