Patent US4196056A successfully refreshed from Google Patents.
Patent US4923542A successfully refreshed from Google Patents.
← Back to Patent Explorer
US5530271A Expired / Lapsed US ⏱️ 0.0 years remaining

Integrated structure active clamp for the protection of power semiconductor devices against overvoltages

Assignee: CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
•
Filing: 1994-12-12
•
Granted: 1996-06-25
•
Expires: 2014-12-12
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An integrated structure active clamp for the protection of a semiconductor power device against overvoltages includes at least one first diode and at least one second diode defined in a lightly doped layer of a first conductivity type in which the power device is also disposed. The first diode has a first electrode connected to a control electrode of the power device and a second electrode connected to a second electrode of the second diode. The second diode has a first electrode connected to a load driving electrode of the power device. The second electrode of the second diode is represented by a first buried region of a second conductivity type, which is buried in the lightly doped layer, and the first electrode of the second diode is represented by a first doped region of the first conductivity type which extends from a semiconductor top surface into the lightly doped layer to partially overlap the first buried region.

Inventors

  • 👤 Piero G. Fallica

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 13:58
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/611

Claims Analysis

Total Claims: 16
Claim 1
Independent Claim 154 words
An integrated structure active clamp for protection of a power semiconductor device against overvoltages, comprising a first diode and a second diode defined in a lightly doped layer of a first conductivity type in which the power semiconductor device is also disposed, the first diode having a first contact connected to a control electrode of the power device and a second contact connected to a second contact of the second diode, a first contact of said second diode being connected to a load driving electrode of the power device, wherein the second contact of the second diode includes a first buried region of a second conductivity type which is buried in the lightly doped layer and the first contact of the second diode includes a first doped region of the first conductivity type which extends from a top surface of the semiconductor into the lightly doped layer to partially overlap the first buried region.
Claim 2
Dependent Claim 154 words
An integrated structure active clamp for protection of a power semiconductor device against overvoltages, comprising a first diode and a second diode defined in a lightly doped layer of a first conductivity type in which the power semiconductor device is also disposed, the first diode having a first contact connected to a control electrode of the power device and a second contact connected to a second contact of the second diode, a first contact of said second diode being connected to a load driving electrode of the power device, wherein the second contact of the second diode includes a first buried region of a second conductivity type which is buried in the lightly doped layer and the first contact of the second diode includes a first doped region of the first conductivity type which extends from a top surface of the semiconductor into the lightly doped layer to partially overlap the first buried region.
Claim 3
Dependent Claim 41 words
The integrated structure active clamp according to claim 1, wherein said first buried region is merged with a first heavily doped deep region of the second conductivity type constituting a contact region disposed below the second contact of the second diode.
Claim 4
Dependent Claim 53 words
The integrated structure active clamp according to claim 1, wherein said first buried region is merged with a lightly doped annular region of the second conductivity type which surrounds a first heavily doped deep region of the second conductivity type constituting a contact region disposed below the second contact of the second diode.
Claim 5
Dependent Claim 132 words
The integrated structure active clamp according to anyone of claim 1, wherein the second contact of the first diode includes a second buried region of the second conductivity type which is buried in the lightly doped layer and the first contact of the first diode includes a second doped region of the first conductivity type which extends from the semiconductor top surface to the second buried region, said second doped region having a dopant concentration between a dopant concentration in the lightly doped layer and a dopant concentration in the second buried region, so as to reduce a gain of a parasitic bipolar transistor, of the first diode, having an emitter, a base and a collector respectively represented by the second doped region, the second buried region and the lightly doped layer.
Claim 6
Dependent Claim 43 words
The integrated structure active clamp according to claim 4, wherein said second buried region is surrounded by and merged with a heavily doped deep annular region of the second conductivity type constituting a contact region to the second contact of the first diode.
Claim 7
Dependent Claim 22 words
The integrated structure active clamp according to anyone of claims 1 to 5, wherein the power semiconductor device is a power MOSFET.
Claim 8
Dependent Claim 24 words
The integrated structure active clamp according to anyone of claims 1 to 5, wherein the power semiconductor device is an Insulated Gate Bipolar Transistor.
Claim 9
Dependent Claim 24 words
The integrated structure active clamp according to anyone of claims 1 to 5, wherein the power semiconductor device is a power Bipolar Junction Transistor.
Claim 10
Dependent Claim 39 words
The integrated structure active clamp according to anyone of claims 1 to 8, wherein said first conductivity type regions are semiconductor regions doped with donor impurities and said second conductivity type regions are semiconductor regions doped with acceptor impurities.
Claim 11
Dependent Claim 39 words
The integrated structure active clamp according to anyone of claims 1 to 8 wherein said first conductivity type regions are semiconductor regions doped with acceptor impurities, and said second conductivity type regions are semiconductor regions doped with donor impurities.
Claim 12
Dependent Claim 165 words
An active clamp for protecting a power semiconductor device against overvoltages, comprising a first diode, a second diode and the power semiconductor device disposed in an epitaxial layer of a first conductivity type, the first diode having a cathode metallization contact connected to a gate electrode of the power device and an anode metallization contact connected to an anode metallization contact of the second diode, a chathode metallization contact of the second diode is connected to a drain electrode of the power device, wherein the anode of the second diode includes a first buried region, of a second conductivity type, which is buried in the epitaxial layer and the cathode of the second diode includes a first doped region, of the first conductivity type, which extends from a top surface of the epitaxial layer into the epitaxial layer to partially overlap the first buried region such that the second diode is formed to be independent of a thickness and a resistivity of the epitaxial layer.
Claim 13
Dependent Claim 165 words
An active clamp for protecting a power semiconductor device against overvoltages, comprising a first diode, a second diode and the power semiconductor device disposed in an epitaxial layer of a first conductivity type, the first diode having a cathode metallization contact connected to a gate electrode of the power device and an anode metallization contact connected to an anode metallization contact of the second diode, a chathode metallization contact of the second diode is connected to a drain electrode of the power device, wherein the anode of the second diode includes a first buried region, of a second conductivity type, which is buried in the epitaxial layer and the cathode of the second diode includes a first doped region, of the first conductivity type, which extends from a top surface of the epitaxial layer into the epitaxial layer to partially overlap the first buried region such that the second diode is formed to be independent of a thickness and a resistivity of the epitaxial layer.
Claim 14
Dependent Claim 31 words
The active clamp of claim 11, wherein a breakdown voltage of the second diode is controlled by a dopant concentration and dimension of the first buried region of the second diode.
Claim 15
Dependent Claim 74 words
The active clamp of claim 11, wherein a clamping voltage of the active clamp is tightly controlled by controlling a dopant concentration and a dimension of the first buried region so as to produce a breakdown voltage which is sufficient to allow a driving signal to be applied to the gate electrode of the power device without causing the second diode to breakdown when the power device is switched on by the driving signal.
Claim 16
Dependent Claim 108 words
The active clamp according to claim 11, wherein the anode of the first diode includes a second buried region, of the second conductivity type, buried in the epitaxial layer and the cathode of the first electrode includes a second doped region, of the first conductivity type, which extends from the top surface of the epitaxial layer to the second buried region, so that a breakdown voltage of the power device is not reduced by a gain of a parasitic bipolar transistor, of the first diode, having an emitter, a base and a collector corresponding, respectively, to the second doped region, the second buried region and the epitaxial layer.

References Cited (Backward Citations)

FR2146323A1 Cited
US3806773A Cited
EP0102696A2 Cited
EP0296675A2 Cited
JPH01157575A Cited
JPH02230774A Cited
EP0437939A1 Cited
US5162966A Cited
JPH04291767A Cited
US5221850A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-06-25 1999-12-25 2000-06-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-06-25 2003-12-25 2004-06-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-06-25 2007-12-25 2008-06-25 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag