LOCOS technology with reduced junction leakage

Claim 1

The method of forming a device isolation region of an integrated circuit with reduced junction leakage comprising: providing an insulating layer over the surface of a silicon substrate; depositing a silicon nitride layer overlying said insulating layer; depositing a silicon dioxide layer overlying said silicon nitride layer; etching away portions of said silicon dioxide, said silicon nitride, and said insulating layers not covered by a mask to provide an opening to said silicon substrate where said device isolation region is to be formed; forming silicon nitride spacers on the sidewalls of said opening; selectively ion implanting channel-stops through said opening into said substrate underneath said opening; oxidizing said silicon substrate within said opening wherein said silicon substrate is transformed to silicon dioxide to form said device isolation region and wherein stress-generated crystalline defects are formed underlying said device isolation region at the edges of said opening; removing said silicon nitride spacers; implanting ions with energy high enough so that said ions form implanted regions deep enough into said silicon substrate wherein said crystalline defects are enclosed within said implanted regions and wherein the enclosure of said crystalline defects within said implanted regions reduces junction leakage wherein said ions are implanted through a mask consisting of said silicon nitride layer, said silicon dioxide layer, said device isolation region, and an additional photoresist with a polysilicon pattern to provide said implanted regions around said device isolation region and at the edges of said device isolation region and to prevent said implanted regions from being present under polysilicon lines to be defined in a later process step; and removing said silicon dioxide, silicon nitride, and said insulating layers completing said device isolation of said integrated circuit.

Claim 2

The method of forming a device isolation region of an integrated circuit with reduced junction leakage comprising: providing an insulating layer over the surface of a silicon substrate; depositing a silicon nitride layer overlying said insulating layer; depositing a silicon dioxide layer overlying said silicon nitride layer; etching away portions of said silicon dioxide, said silicon nitride, and said insulating layers not covered by a mask to provide an opening to said silicon substrate where said device isolation region is to be formed; forming silicon nitride spacers on the sidewalls of said opening; selectively ion implanting channel-stops through said opening into said substrate underneath said opening; oxidizing said silicon substrate within said opening wherein said silicon substrate is transformed to silicon dioxide to form said device isolation region and wherein stress-generated crystalline defects are formed underlying said device isolation region at the edges of said opening; removing said silicon nitride spacers; implanting ions with energy high enough so that said ions form implanted regions deep enough into said silicon substrate wherein said crystalline defects are enclosed within said implanted regions and wherein the enclosure of said crystalline defects within said implanted regions reduces junction leakage wherein said ions are implanted through a mask consisting of said silicon nitride layer, said silicon dioxide layer, said device isolation region, and an additional photoresist with a polysilicon pattern to provide said implanted regions around said device isolation region and at the edges of said device isolation region and to prevent said implanted regions from being present under polysilicon lines to be defined in a later process step; and removing said silicon dioxide, silicon nitride, and said insulating layers completing said device isolation of said integrated circuit.

Claim 8

The method of forming a field oxidation region of an integrated circuit with reduced junction leakage comprising: providing a pad silicon oxide layer over the surface of a silicon substrate; depositing a silicon nitride layer overlying said pad silicon oxide layer; depositing a silicon dioxide layer overlying said silicon nitride layer; etching away portions of said silicon dioxide, said silicon nitride, and said pad silicon oxide layers not covered by a mask to provide an opening to said silicon substrate where said field oxidation region is to be formed; forming silicon nitride spacers on the sidewalls of said opening; selectively ion implanting channel-stops through said opening into said substrate underneath said opening; oxidizing said silicon substrate within said opening wherein said silicon substrate is transformed to silicon dioxide to form said field oxidation region and wherein stress-generated crystalline defects are formed underlying said field oxidation region at the edges of said opening; removing said silicon nitride spacers; implanting ions with energy high enough so that said ions form implanted regions deep enough into said silicon substrate wherein said crystalline defects are enclosed within said implanted regions and wherein the enclosure of said crystalline defects within said implanted regions reduces junction leakage wherein said ions are implanted through a mask consisting of said silicon nitride layer, said silicon dioxide layer, said device isolation region, and an additional photoresist with a polysilicon pattern to provide said implanted regions around said device isolation region and at the edges of said device isolation region and to prevent said implanted regions from being present under polysilicon lines to be defined in a later process step; and removing said silicon dioxide, silicon nitride, and said pad silicon oxide layers completing said field oxidation of said integrated circuit.

Claim 9

The method of forming a field oxidation region of an integrated circuit with reduced junction leakage comprising: providing a pad silicon oxide layer over the surface of a silicon substrate; depositing a silicon nitride layer overlying said pad silicon oxide layer; depositing a silicon dioxide layer overlying said silicon nitride layer; etching away portions of said silicon dioxide, said silicon nitride, and said pad silicon oxide layers not covered by a mask to provide an opening to said silicon substrate where said field oxidation region is to be formed; forming silicon nitride spacers on the sidewalls of said opening; selectively ion implanting channel-stops through said opening into said substrate underneath said opening; oxidizing said silicon substrate within said opening wherein said silicon substrate is transformed to silicon dioxide to form said field oxidation region and wherein stress-generated crystalline defects are formed underlying said field oxidation region at the edges of said opening; removing said silicon nitride spacers; implanting ions with energy high enough so that said ions form implanted regions deep enough into said silicon substrate wherein said crystalline defects are enclosed within said implanted regions and wherein the enclosure of said crystalline defects within said implanted regions reduces junction leakage wherein said ions are implanted through a mask consisting of said silicon nitride layer, said silicon dioxide layer, said device isolation region, and an additional photoresist with a polysilicon pattern to provide said implanted regions around said device isolation region and at the edges of said device isolation region and to prevent said implanted regions from being present under polysilicon lines to be defined in a later process step; and removing said silicon dioxide, silicon nitride, and said pad silicon oxide layers completing said field oxidation of said integrated circuit.

Claim 15

The method of forming a field oxidation region of an integrated circuit with reduced junction leakage comprising: providing a pad silicon oxide layer over the surface of a silicon substrate; depositing a silicon nitride layer overlying said pad silicon oxide layer; etching away portions of said silicon nitride and said pad silicon oxide layers not covered by a mask to provide an opening to said silicon substrate where said field oxidation region is to be formed; selectively ion implanting channel-stops through said opening into said substrate underneath said opening; oxidizing said silicon substrate within said opening wherein said silicon substrate is transformed to silicon dioxide to form said field oxidation region and wherein stress-generated crystalline defects are formed underlying said field oxidation region at the edges of said opening; coating the surface of said substrate with a planarizing layer; removing portions of said planarizing layer above the top surface of said field oxidation region; removing said silicon nitride layer not covered by said remaining planarizing layer; implanting ions with energy high enough so that said ions form implanted regions deep enough into said silicon substrate wherein said crystalline defects are enclosed within said implanted regions and wherein the enclosure of said crystalline defects within said implanted regions reduces junction leakage; removing said silicon nitride and said pad silicon oxide layers completing said field oxidation of said integrated circuit.

Claim 16

The method of forming a field oxidation region of an integrated circuit with reduced junction leakage comprising: providing a pad silicon oxide layer over the surface of a silicon substrate; depositing a silicon nitride layer overlying said pad silicon oxide layer; etching away portions of said silicon nitride and said pad silicon oxide layers not covered by a mask to provide an opening to said silicon substrate where said field oxidation region is to be formed; selectively ion implanting channel-stops through said opening into said substrate underneath said opening; oxidizing said silicon substrate within said opening wherein said silicon substrate is transformed to silicon dioxide to form said field oxidation region and wherein stress-generated crystalline defects are formed underlying said field oxidation region at the edges of said opening; coating the surface of said substrate with a planarizing layer; removing portions of said planarizing layer above the top surface of said field oxidation region; removing said silicon nitride layer not covered by said remaining planarizing layer; implanting ions with energy high enough so that said ions form implanted regions deep enough into said silicon substrate wherein said crystalline defects are enclosed within said implanted regions and wherein the enclosure of said crystalline defects within said implanted regions reduces junction leakage; removing said silicon nitride and said pad silicon oxide layers completing said field oxidation of said integrated circuit.