Process of fabricating DRAM storage capacitors

Claim 1

A method for constructing a memory cell on a surface of a substrate, comprising the steps of: (a) forming a transistor having gate electrode and source/drain regions on said surface of said substrate; (b) forming a first conductive layer over said transistor structure, said first conductive layer being coupled to one of said source/drain regions; (c) forming a mask to cover a planned capacitor area, and then removing non-masked portions of said first conductive layer; (d) applying an oxide by liquid phase selective deposition over the non-masked portions of said first conductive layer, and then removing said mask to expose a sidewall defined by said oxide; (e) forming a conductive sidewall spacer on the sidewall of said oxide, said conductive sidewall spacer connecting with a remainder of said first conductive layer so that said sidewall spacer and remainder of the first conductive layer together form a first capacitor electrode; (f) removing said oxide; (g) forming a storage layer along the surface of said first capacitor electrode; and (h) forming a second capacitor electrode along the surface of said storage layer.

Claim 2

A method for constructing a memory cell on a surface of a substrate, comprising the steps of: (a) forming a transistor having gate electrode and source/drain regions on said surface of said substrate; (b) forming a first conductive layer over said transistor structure, said first conductive layer being coupled to one of said source/drain regions; (c) forming a mask to cover a planned capacitor area, and then removing non-masked portions of said first conductive layer; (d) applying an oxide by liquid phase selective deposition over the non-masked portions of said first conductive layer, and then removing said mask to expose a sidewall defined by said oxide; (e) forming a conductive sidewall spacer on the sidewall of said oxide, said conductive sidewall spacer connecting with a remainder of said first conductive layer so that said sidewall spacer and remainder of the first conductive layer together form a first capacitor electrode; (f) removing said oxide; (g) forming a storage layer along the surface of said first capacitor electrode; and (h) forming a second capacitor electrode along the surface of said storage layer.

Claim 8

A method for constructing a memory cell on a surface of a substrate, comprising the steps of: forming a transistor having gate electrode and source/drain regions on said surface of said substrate; forming a first capacitor electrode coupled to one of said source/drain regions, said first capacitor electrode including a bottom portion and a substantially upright portion extending away from said bottom portion, the step of forming the first capacitor electrode comprising forming a conductive layer over said transistor, said conductive layer being coupled to one of said source/drain regions, forming a mask to cover a planned capacitor area, and then removing a non-masked portion of said conductive layer so that a remaining conductive layer forms said bottom portion of said first capacitor electrode, selectively depositing an oxide on the non-masked area, then removing said mask, and forming a conductive sidewall spacer on the sidewalls of said selectively deposited oxide to construct said substantially upright portion of said first capacitor electrode; forming a storage layer along the surface of said first capacitor electrode; and forming a second capacitor electrode along the surface of said storage layer.

Claim 9

A method for constructing a memory cell on a surface of a substrate, comprising the steps of: forming a transistor having gate electrode and source/drain regions on said surface of said substrate; forming a first capacitor electrode coupled to one of said source/drain regions, said first capacitor electrode including a bottom portion and a substantially upright portion extending away from said bottom portion, the step of forming the first capacitor electrode comprising forming a conductive layer over said transistor, said conductive layer being coupled to one of said source/drain regions, forming a mask to cover a planned capacitor area, and then removing a non-masked portion of said conductive layer so that a remaining conductive layer forms said bottom portion of said first capacitor electrode, selectively depositing an oxide on the non-masked area, then removing said mask, and forming a conductive sidewall spacer on the sidewalls of said selectively deposited oxide to construct said substantially upright portion of said first capacitor electrode; forming a storage layer along the surface of said first capacitor electrode; and forming a second capacitor electrode along the surface of said storage layer.