US5528608A
Expired / Lapsed
US
⏱️ 0.0 years remaining
De-interleave circuit for regenerating digital data
Assignee: Sony Corp
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Filing: 1995-04-07
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Granted: 1996-06-18
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Expires: 2015-04-07
Abstract
Abstract In a digital data regenerating apparatus for regenerating digital data, while correcting errors in the data, which is formed of a predetermined number of words corresponding to 1 frame and input in parallel, a de-interleave circuit comprises a demodulator circuit for demodulating digital data, a buffer RAM for temporarily storing demodulated output data output from the demodulator circuit, an error correcting circuit for receiving data from the buffer RAM through an input circuit, a microprogram sequencer, and a pointer setting circuit controlled by the microprogram sequencer. An error correcting flag is correspondently set up for each set of data formed of a plurality of words and, in a plurality of operating modes in which an error correcting flag is attached to each set of different data, the addresses for setting data to the pointers are made different such that error correction is achieved by the use of a common microprogram in the plurality of operating modes.
Inventors
- 👤 Kazutoshi Shimizume
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 17:44
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1806; G11B20/1809; H; H03; H03M; H03M13/00; H03M13/27
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
119 words
In a digital data regenerating apparatus for regenerating digital data, while correcting errors in the data, which is formed of a predetermined number of words corresponding to 1 frame and input in parallel, a de-interleave circuit comprising: a demodulator circuit for demodulating digital data; a buffer RAM for temporarily storing demodulated output data output from said demodulator circuit; an error correcting circuit for receiving data from said buffer RAM through an input circuit; a microprogram sequencer; and a plurality of pointers and a pointer setting circuit for setting said pointers controlled by said microprogram sequencer, wherein each of a plurality of error correcting pointers is set to the same address corresponding to data formed of a plurality of words.
Claim 2
Dependent Claim
119 words
In a digital data regenerating apparatus for regenerating digital data, while correcting errors in the data, which is formed of a predetermined number of words corresponding to 1 frame and input in parallel, a de-interleave circuit comprising: a demodulator circuit for demodulating digital data; a buffer RAM for temporarily storing demodulated output data output from said demodulator circuit; an error correcting circuit for receiving data from said buffer RAM through an input circuit; a microprogram sequencer; and a plurality of pointers and a pointer setting circuit for setting said pointers controlled by said microprogram sequencer, wherein each of a plurality of error correcting pointers is set to the same address corresponding to data formed of a plurality of words.
Claim 3
Dependent Claim
82 words
A de-interleave circuit according to claim 1, wherein, in a plurality of operating modes in which an error correcting flag is attached to each set of different data, addresses for setting data to said pointers are made different wherein in one mode a plurality of pointers are set to the same address and in another mode said pointers are set to different addresses, such that error correction is achieved by the use of a common microprogram in said plurality of operating modes.
Claim 4
Dependent Claim
27 words
The de-interleave circuit according to claim 1, wherein said buffer RAM temporarily stores said pointers each of which correspond to data formed of a plurality of words.
Claim 5
Dependent Claim
60 words
The de-interleave circuit according to claim 1, wherein said de-interleave circuit has means for designating operation in a plurality of modes including a CD mode and a MD mode, said plurality of pointers including C1 pointers and C2 pointers, and said pointer setting circuit setting said C2 pointers different in said CD mode from their setting in said MD mode.
Claim 6
Dependent Claim
26 words
The de-interleave circuit according to claim 4, wherein said microprogram sequencer executes a common error correcting program in both said CD mode and said MD mode.
Claim 7
Dependent Claim
36 words
The de-interleave circuit according to claim 1, wherein said pointer setting circuit incorporates an error correcting circuit interconnected to said demodulated circuit over a local bus, and a pointer processing circuit connected to said local bus.
Claim 8
Dependent Claim
87 words
The de-interleave circuit according to claim 6, wherein said pointer processing circuit comprises a plurality of flip/flops having their inputs connected to said local bus, each of said flip/flops having an enable input connected to a signal which enables signals to be read from said local bus into a data input of each of said flip/flops, and a plurality of output buffers connected between outputs of each of said flip/flops and said local bus for allowing signals to be written from said flip/flops onto said local bus.
Claim 9
Dependent Claim
72 words
The de-interleave circuit according to claim 1, wherein said pointer setting circuit incorporates a pointer processing circuit having a plurality of registers connected to said buffer RAM for receiving therefrom and storing a low order pointer PL and high order pointer PU, a pair of latch circuits for latching the low order pointer PL and the high order pointer PU respectively, and a matrix circuit interconnected between said registers and said latches.
Claim 10
Dependent Claim
34 words
The de-interleave circuit according to claim 8, including a counter for controlling operation of said matrix, and a source of timing pulses for controlling operation of said counter and for simultaneously enabling said registers.
Claim 11
Dependent Claim
36 words
A de-interleave circuit according to claim 1, wherein said addresses correspond to addresses in said buffer RAM, and the capacity of said buffer RAM is reduced because a plurality of said pointers share the same addresses.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-18 | 1999-12-18 | 2000-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-18 | 2003-12-18 | 2004-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-18 | 2007-12-18 | 2008-06-18 | $7700.00 | Window Closed / Lapsed |