EP0472415A2
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EP
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Error correction encoding apparatus
Assignee: Sony Corp
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Filing: 1991-08-21
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Granted: —
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Expires: 2011-08-21
Abstract
Abstract An error correction encoding apparatus (30), for use for example in an optical disc recording and/or reproducing apparatus, comprises a first delay circuit (32) that applies different amounts of delay to respective data words constituting a data block to convert input data in a first array state into a second array state. A first error correction encoder (33) generates first check words from the data in the second array state. A second delay circuit (34) applies different amounts of delay to the data in the second array state and to the first check words to provide data and check words in a third array state. A second error correction encoder (35) generates second check words from the data and check words in the third array state. The amounts of delay applied by the first and second delay circuits (32, 34) are such that the array state of the data in the third array state is the same as the array state of the data in the first array state.
Inventors
- 👤 Yasuaki C/O Patents Division Maeda
- 👤 Kazuhiko C/O Patents Division Fujiie
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 17:57
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1806; G11B20/1809
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
222 words
An error correction encoding apparatus (30; 50) for processing an input data word series with encoding for error correction, the apparatus comprising: first delay means (32; 52) for applying different amounts of delay to respective data words constituting a data block for converting the input data word series in a first array state into an input data word series in a second array state; first error correction encoding means (33; 53) for generating a first check words series from the data word series in said second array state; second delay means (34; 54) for applying different amounts of delay to the data word series in said second array state and to the first check word series for converting said data word series and said check word series into a data word series and a check word series in a third array state; and second error correction encoding means (35; 55) for generating a second check word series from said data word series and said check word series in the third array state; the amounts of delay applied by said first and second delay means (32, 34; 52, 54) being set so that the array state of said data word series in said third array state is the same as the array state of said data word series in said first array state.
Claim 2
Dependent Claim
89 words
Apparatus according to claim 1, comprising third delay means (31; 51) for applying the same amount of delay to one of even-numbered data words and odd-numbered data words of said data word series in said first array state, and fourth delay means (36; 56) for applying the same amount of delay as that applied by said third delay means (31; 51) to the other of said even-numbered data words and said odd-numbered data words of said data word series and the check word series in said third array state.
Claim 3
Dependent Claim
25 words
Apparatus according to claim 2, comprising sign-inverting means for inverting the signs of said first and second check word series in said third array state.
Claim 4
Dependent Claim
24 words
Apparatus according to claim 1, claim 2 or claim 3, wherein said first and second check word series are parity codes of Reed-Solomon codes.
Claim 5
Dependent Claim
26 words
Apparatus according to any one of claims 1 to 4, which is capable of processing a said input data word series in a data compressed state.
Claim 6
Dependent Claim
381 words
An error correction encoding apparatus which is so operative that different amounts of delay (32; 52) are applied to data words constituting a data block of a data word series in a first array state for converting said data word series into a data word series in a second array state, first check word series are generated (33; 53) from the data word series in said second array state, different amounts of delay (34; 54) are applied to said data word series and said first check word series in said second array state for converting said data word series and said check word series into a data word series and a check word series in a third array state, second check word series are generated (35; 55) from the data word series and the check word series in the third array state, and an error correction decoding operation (40; 60) is executed on an input data word series on which error correction encoding has been executed so that the data word series in said third array state is equal to the array state of said data word series in said first array state, said apparatus comprising: first error correction decoding means (42; 62) for processing the data word series constituting a data block of the input data word series in said third array state and the first check word series by error correction by an error correction code (C1) using said second check word series; first delay means (43; 63) for applying different amounts of delay to said data word series and the check word series corrected for errors by said first error correction decoding means (42; 62) for converting said data word series and the first check word series into the data word series and the first check word series in said second array state; second error correcting decoding means (44; 64) for error-correcting said data word series in said second array state by an error correction code (C2) using said first check word series; and second delay means (45; 65) for applying different amounts of delay to said data word series corrected for errors by said second error correcting decoding means (44; 64) for converting said data word series into a data word series in said first array state.
Claim 7
Dependent Claim
90 words
Apparatus according to claim 6, comprising third delay means (41; 61) for applying the same amount of delay to one of even-numbered data words and check words and odd-numbered data words and check words of said data word series in said third array state, and fourth delay means (45; 65) for applying the same amount of delay as that applied by said third delay means (41; 61) to the other of said even-numbered data words and said odd-numbered data words of said data word series in said third array state.
Claim 8
Dependent Claim
25 words
Apparatus according to claim 7, comprising sign-inverting means for inverting the signs of said first and second check word series in said third array state.
Claim 9
Dependent Claim
24 words
Apparatus according to claim 6, claim 7 or claim 8, wherein said first and second check word series are parity codes of Reed-Solomon codes.
Claim 10
Dependent Claim
30 words
Apparatus according to any one of claims 6 to 9, which is capable of executing error correction decoding on a said input data word series in a data compressed state.
Claim 11
Dependent Claim
30 words
Apparatus according to any one of claims 6 to 10, which is capable of executing error correction decoding on a said input data word series reproduced from a recording medium.
References Cited (Backward Citations)
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