Memory with latched output

Claim 2

A Random Access Memory, comprising: a) a plurality of data cells, each of which produces DATA, when selected, or a DATA ABSENT signal, when not selected; and b) sense means for isolating an output line, in response to the DATA ABSENT signal.

Claim 3

Memory in a computer, comprising: a) a plurality of memory cells, i) each having an ENABLE input which allows contents of a cell to reach a cell output, and ii) each having a differential output D and D, and producing A) a first differential signal pair on D and D when a ONE is stored in the cell and the cell is ENABLED; B) a second differential signal pair on D and D when a ZERO is stored in the cell and the cell is ENABLED; C) a third differential signal pair on D and D when the cell is not ENABLED; b) a sense amplifier for each memory cell, comprising a first and second differential amplifier each having (+) and (-) inputs, connected such that the D output connects to the (+) input of the first differential amplifier and the (-) input of the second differential amplifier; and the D output connects to the (-) input of the first differential amplifier and the (+) input of the second differential amplifier; c) a p-channel FET in series with an n-channel FET for each sense amplifier, with the drain of the n-channel FET connected to the drain of the p-channel FET, and connected such that the gate of the p-channel FET connects to the output of the respective first differential amplifier, and the gate of the n-channel FET connects to the output of an inverter whose input connects to the output of the second respective differential amplifier; and d) a common output line connected to the drains of all n-channel FETs in element c).

Claim 4

Memory in a computer, comprising: a) a plurality of memory cells, i) each having an ENABLE input which allows contents of a cell to reach a cell output, and ii) each having a differential output D and D, and producing A) a first differential signal pair on D and D when a ONE is stored in the cell and the cell is ENABLED; B) a second differential signal pair on D and D when a ZERO is stored in the cell and the cell is ENABLED; C) a third differential signal pair on D and D when the cell is not ENABLED; b) a sense amplifier for each memory cell, comprising a first and second differential amplifier each having (+) and (-) inputs, connected such that the D output connects to the (+) input of the first differential amplifier and the (-) input of the second differential amplifier; and the D output connects to the (-) input of the first differential amplifier and the (+) input of the second differential amplifier; c) a p-channel FET in series with an n-channel FET for each sense amplifier, with the drain of the n-channel FET connected to the drain of the p-channel FET, and connected such that the gate of the p-channel FET connects to the output of the respective first differential amplifier, and the gate of the n-channel FET connects to the output of an inverter whose input connects to the output of the second respective differential amplifier; and d) a common output line connected to the drains of all n-channel FETs in element c).

Claim 5

A Random Access Memory (RAM), comprising: a) a plurality of memory cells, each of which produces: i) first data signals when the cell stores a ONE and the cell is selected; and ii) second data signals when the cell stores a ZERO and the cell is selected; and iii) third data signals when the cell is not selected; b) a sense amplifier for each memory cell which produces: i) a first pair of signals in response to the first data signals, when the sense amplifier is selected; ii) a second pair of signals in response to .the second data signals, when the sense amplifier is selected; and iii) a third pair of signals in response to the third data signals, whether or not the sense amplifier is selected; and c) a driver for each sense amplifier, which applies i) a first output signal to an output line, in response to said first pair of signals from the respective sense amplifier; ii) a second output signal to said output line, in response to said second pair of signals from the respective sense amplifier; and iii) no signal to said output line, in response to said third pair of signals from the respective sense amplifier.

Claim 6

A Random Access Memory (RAM), comprising: a) a plurality of memory cells, each of which produces: i) first data signals when the cell stores a ONE and the cell is selected; and ii) second data signals when the cell stores a ZERO and the cell is selected; and iii) third data signals when the cell is not selected; b) a sense amplifier for each memory cell which produces: i) a first pair of signals in response to the first data signals, when the sense amplifier is selected; ii) a second pair of signals in response to .the second data signals, when the sense amplifier is selected; and iii) a third pair of signals in response to the third data signals, whether or not the sense amplifier is selected; and c) a driver for each sense amplifier, which applies i) a first output signal to an output line, in response to said first pair of signals from the respective sense amplifier; ii) a second output signal to said output line, in response to said second pair of signals from the respective sense amplifier; and iii) no signal to said output line, in response to said third pair of signals from the respective sense amplifier.