US5525825A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Monolithic integrated circuit with at least one CMOS field-effect transistor and one npn bipolar transistor
Assignee: TDK Micronas GmbH
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Filing: 1995-01-12
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Granted: 1996-06-11
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Expires: 2015-01-12
Abstract
Abstract The invention relates to a method of making a monolithic integrated circuit with at least one CMOS field-effect transistor and one npn bipolar transistor wherein a thin oxide layer is covered with a protective polysilicon layer in both the bipolar-transistor area and the field-effect-transistor area.
Inventors
- 👤 Juergen Nagel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 01:33
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
175 words
A monolithic integrated circuit having at least one pair of CMOS field-effect transistors and at least one planar bipolar transistor, comprising: a substrate of a first conductivity having a well portion of a second conductivity extending into said substrate from a first surface thereof; a base region extending into said well portion from said first surface; an emitter area extending into said base region from said first surface; a first patterned oxide layer covering selected areas of said base region and said emitter area; a second patterned oxide layer having a thickness which is substantially greater than said first oxide layer, said second oxide layer having portions which are laterally separated from said base region by collector regions of said well portion; a patterned polysilicon layer which defines transition areas between said base and said collector regions, said polysilicon layer having a portion disposed over said first oxide layer, wherein said first oxide layer electrically isolates said portion of said polysilicon layer from said transition areas; and a titanium-silicide layer selectively covering said polysilicon layer.
Claim 2
Dependent Claim
175 words
A monolithic integrated circuit having at least one pair of CMOS field-effect transistors and at least one planar bipolar transistor, comprising: a substrate of a first conductivity having a well portion of a second conductivity extending into said substrate from a first surface thereof; a base region extending into said well portion from said first surface; an emitter area extending into said base region from said first surface; a first patterned oxide layer covering selected areas of said base region and said emitter area; a second patterned oxide layer having a thickness which is substantially greater than said first oxide layer, said second oxide layer having portions which are laterally separated from said base region by collector regions of said well portion; a patterned polysilicon layer which defines transition areas between said base and said collector regions, said polysilicon layer having a portion disposed over said first oxide layer, wherein said first oxide layer electrically isolates said portion of said polysilicon layer from said transition areas; and a titanium-silicide layer selectively covering said polysilicon layer.
Claim 3
Dependent Claim
24 words
The monolithic integrated circuit of claim 1, wherein said first conductivity is n-type, said second conductivity is p-type and said bipolar transistor is npn.
Claim 4
Dependent Claim
24 words
The monolithic integrated circuit of claim 1, wherein said first conductivity is p-type, said second conductivity is n-type and said bipolar transistor is pnp.
Claim 5
Dependent Claim
15 words
The monolithic integrated circuit of claim 1, wherein said polysilicon layer is doped with arsenic.
Claim 6
Dependent Claim
15 words
The monolithic integrated circuit of claim 1, wherein said polysilicon layer is doped with phosphorous.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-11 | 1999-12-11 | 2000-06-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-11 | 2003-12-11 | 2004-06-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-11 | 2007-12-11 | 2008-06-11 | $7700.00 | Window Closed / Lapsed |