Method of making a low voltage coefficient capacitor

Claim 1

A method of fabricating a capacitor having substantially uniform parasitic effects over an operating range, said method comprising the steps of: forming a first conductive layer superjacent a buried oxide layer, said buried oxide layer being formed superjacent a semiconductor substrate, said first conductive layer comprising heavily doped silicon and having a first conductivity type and said substrate comprising a second conductivity type opposite of said first conductivity type, said first conductive layer having an exposed upper surface region and a thickness substantially in the range of 0.1 μm to 10 μm; implanting said exposed upper surface region of said first conductive layer with a dopant having said first conductivity type; forming a trench surrounding said first conductive layer, said trench having a width substantially in the range of 0.2 μm to 4 μm and a thickness substantially equivalent to said first conductive layer; filling said trench with a dielectric material comprising silicon dioxide or silicon dioxide in combination with polysilicon; forming a gate oxide layer superjacent said exposed upper surface of said first conductive layer, said gate oxide layer having a thickness substantially in the range of 4000 Å to 8000 Å; and forming a second conductive layer superjacent said gate oxide layer, said second conductive layer comprising heavily doped polysilicon and having a thickness substantially in the range of 1500 Å to 5500 Å, thereby forming a capacitor having substantially uniform parasitic effects over an operating voltage range of the semiconductor.

Claim 2

A method of fabricating a capacitor having substantially uniform parasitic effects over an operating range, said method comprising the steps of: forming a first conductive layer superjacent a buried oxide layer, said buried oxide layer being formed superjacent a semiconductor substrate, said first conductive layer comprising heavily doped silicon and having a first conductivity type and said substrate comprising a second conductivity type opposite of said first conductivity type, said first conductive layer having an exposed upper surface region and a thickness substantially in the range of 0.1 μm to 10 μm; implanting said exposed upper surface region of said first conductive layer with a dopant having said first conductivity type; forming a trench surrounding said first conductive layer, said trench having a width substantially in the range of 0.2 μm to 4 μm and a thickness substantially equivalent to said first conductive layer; filling said trench with a dielectric material comprising silicon dioxide or silicon dioxide in combination with polysilicon; forming a gate oxide layer superjacent said exposed upper surface of said first conductive layer, said gate oxide layer having a thickness substantially in the range of 4000 Å to 8000 Å; and forming a second conductive layer superjacent said gate oxide layer, said second conductive layer comprising heavily doped polysilicon and having a thickness substantially in the range of 1500 Å to 5500 Å, thereby forming a capacitor having substantially uniform parasitic effects over an operating voltage range of the semiconductor.

Claim 3

A method of fabricating a capacitor on a semiconductor substrate, comprising the steps of: depositing a first dielectric layer on the substrate; forming a first conductive layer superjacent said first dielectric layer, said first conductive layer having an exposed major surface; etching an isolation trench through said first conductive layer to said first dielectric layer, said trench extending along said exposed major surface in a closed path which is circumferential to a segment of said first conductive layer, said segment forming a first plate of the capacitor; filling said trench with a trench dielectric material to create, in combination with said first dielectric layer, a dielectric shell surrounding said first plate on all but said exposed major surface thereof; forming a second dielectric layer superjacent a first surface portion of said exposed major surface of said first plate, a second surface portion thereof remaining exposed; and forming a second conductive layer superjacent said second dielectric layer in a manner which causes said second surface portion of said major surface to remain exposed, said second conductive layer providing a second plate of the capacitor, whereby a capacitor is formed having substantially uniform parasitic effects over an operating voltage range of the semiconductor.

Claim 4

A method of fabricating a capacitor on a semiconductor substrate, comprising the steps of: depositing a first dielectric layer on the substrate; forming a first conductive layer superjacent said first dielectric layer, said first conductive layer having an exposed major surface; etching an isolation trench through said first conductive layer to said first dielectric layer, said trench extending along said exposed major surface in a closed path which is circumferential to a segment of said first conductive layer, said segment forming a first plate of the capacitor; filling said trench with a trench dielectric material to create, in combination with said first dielectric layer, a dielectric shell surrounding said first plate on all but said exposed major surface thereof; forming a second dielectric layer superjacent a first surface portion of said exposed major surface of said first plate, a second surface portion thereof remaining exposed; and forming a second conductive layer superjacent said second dielectric layer in a manner which causes said second surface portion of said major surface to remain exposed, said second conductive layer providing a second plate of the capacitor, whereby a capacitor is formed having substantially uniform parasitic effects over an operating voltage range of the semiconductor.