Patent US5524249A successfully refreshed from Google Patents.
US5524249A
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Video subsystem power management apparatus and method
Assignee: Hewlett Packard Development Co LP
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Filing: 1994-01-27
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Granted: 1996-06-04
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Expires: 2014-01-27
Abstract
Abstract Power is conserved in a video subsystem by inactivating a pixel clock (PCLK) and reducing frequency of a memory clock (MCLK) responsive to an indication of user inactivity. The inactivation of PCLK reduces the power consumed in the RAMDAC, frame buffer, phase lock loop (PLL) clock circuit, and to a smaller extent, the video controller. Reducing the frequency of MCLK conserves power in the video controller and the PLL, In order to maintain the integrity of the data in the frame buffer, the refresh rate programmed by the video controller is increased to offset the reduction of the MCLK frequency. Significant power savings can be accomplished with minimal BIOS or video controller programming and minimal transfer of state information prior to power-down.
Inventors
- 👤 Abdel H. Suboh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:18
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/325; G06F1/3265; G06F1/3206; G06F1/3215; G06F1/3218; G09; G09G; G09G5/00; G09G5/36; G09G2330/00; G09G2330/02; G09G2330/021; G09G2330/022; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
58 words
A method of reducing power consumption in a video subsystem of a computer, comprising the steps of: inactivating a pixel clock which drives a RAMDAC, thereby reducing power consumed by the RAMDAC; and decreasing the frequency of a memory clock for driving a video controller by a predetermined factor, thereby reducing the power consumed by the video controller.
Claim 2
Independent Claim
58 words
A method of reducing power consumption in a video subsystem of a computer, comprising the steps of: inactivating a pixel clock which drives a RAMDAC, thereby reducing power consumed by the RAMDAC; and decreasing the frequency of a memory clock for driving a video controller by a predetermined factor, thereby reducing the power consumed by the video controller.
Claim 3
Dependent Claim
72 words
The method of claim 1 and wherein said video controller refreshes a frame buffer at a programmable rate and further comprising the step of increasing the programmed refresh rate in the video controller by said predetermined factor, such that the reduction in the memory clock frequency to the video controller is offset by the increase in the programmed refresh rate, resulting in the frame buffer being refreshed at a normal refresh rate.
Claim 4
Dependent Claim
41 words
The method of claim 1 wherein said step of inactivating the pixel clock comprises the step of programming a phase lock loop clock circuit to disable generation of the pixel clock signal responsive to a data word from the video controller.
Claim 5
Independent Claim
42 words
The method of claim I wherein said step of decreasing the memory clock frequency comprises the step of programming a phase lock loop clock circuit to output a clock at a predetermined frequency responsive to a data word from the video controller.
Claim 6
Dependent Claim
24 words
The method of claim 1 and further comprising the step of disabling a shift clock to a plurality of VRAMs forming a frame buffer.
Claim 7
Dependent Claim
39 words
The method of claim 1 wherein said step of decreasing the frequency of a memory clock to the video controller thereby reduces the frequency of memory cycles in a frame buffer, reducing the power consumed by the frame buffer.
Claim 8
Independent Claim
78 words
A method of reducing power consumption in a video subsystem of a computer, comprising the steps of: increasing the rate at which a video controller refreshes memory in a frame buffer by a predetermined factor; and decreasing the frequency of a memory clock for driving the video controller by the predetermined factor, thereby reducing the power consumed by the video controller and reducing the frequency of memory cycles to a frame buffer, while maintaining a normal refresh rate.
Claim 9
Independent Claim
78 words
A method of reducing power consumption in a video subsystem of a computer, comprising the steps of: increasing the rate at which a video controller refreshes memory in a frame buffer by a predetermined factor; and decreasing the frequency of a memory clock for driving the video controller by the predetermined factor, thereby reducing the power consumed by the video controller and reducing the frequency of memory cycles to a frame buffer, while maintaining a normal refresh rate.
Claim 10
Dependent Claim
26 words
The method of claim 7 and further comprising the step of inactivating a pixel clock which drives a RAMDAC, thereby reducing power consumed by the RAMDAC.
Claim 11
Dependent Claim
41 words
The method of claim 8 wherein said step of inactivating the pixel clock comprises the step of programming a phase lock loop clock circuit to disable generation of the pixel clock signal responsive to a data word from the video controller,
Claim 12
Dependent Claim
32 words
The method of claim 7 and further comprising the step of inactivating a shift clock for driving the output of said frame buffer responsive to said step of inactivating the pixel clock.
Claim 13
Dependent Claim
42 words
The method of claim 7 wherein said step of decreasing the memory clock frequency comprises the step of programming a phase lock loop clock circuit to output a clock at a predetermined frequency responsive to a data word from the video controller.
Claim 14
Dependent Claim
146 words
Circuitry for providing a video subsystem with power conservation capabilities, comprising: clock circuitry for programmably generating a first clock and a second clock, such that said first clock can be disabled responsive to a first control signal and said second clock can be reduced in frequency responsive to a second control signal; a frame buffer memory; a RAMDAC driven by said first clock coupled to said frame buffer, the power consumed by said RAMDAC dependent upon the frequency of said first clock; a video controller driven by said second clock and coupled to said frame buffer, said video controller controlling memory cycles in said frame buffer responsive to said second clock; and circuitry for inactivating said first clock and reducing the frequency of said second clock responsive to an indication of inactivity to reduce power consumption in said clock circuitry, said frame buffer and said RAMDAC.
Claim 15
Dependent Claim
146 words
Circuitry for providing a video subsystem with power conservation capabilities, comprising: clock circuitry for programmably generating a first clock and a second clock, such that said first clock can be disabled responsive to a first control signal and said second clock can be reduced in frequency responsive to a second control signal; a frame buffer memory; a RAMDAC driven by said first clock coupled to said frame buffer, the power consumed by said RAMDAC dependent upon the frequency of said first clock; a video controller driven by said second clock and coupled to said frame buffer, said video controller controlling memory cycles in said frame buffer responsive to said second clock; and circuitry for inactivating said first clock and reducing the frequency of said second clock responsive to an indication of inactivity to reduce power consumption in said clock circuitry, said frame buffer and said RAMDAC.
Claim 16
Dependent Claim
19 words
The circuitry of claim 12 wherein said video controller comprises circuitry for refreshing the frame buffer at selectable rates.
Claim 17
Dependent Claim
27 words
The circuitry of claim 13 and further comprising circuitry for increasing the refresh rate of the frame buffer prior to reducing the frequency of said second clock.
Claim 18
Dependent Claim
27 words
The circuitry of claim 12 wherein said video controller further comprises circuitry for communicating with said clock circuitry for setting said second clock to a desired frequency.
Claim 19
Dependent Claim
23 words
The circuitry of claim 15 wherein said video controller further comprises circuitry for communicating with said clock circuitry for inactivating said first clock.
Claim 20
Dependent Claim
15 words
The circuitry of claim 12 wherein said frame buffer memory comprises a plurality of VRAMs.
Claim 21
Dependent Claim
15 words
The circuitry of claim 12 wherein said frame buffer memory comprises a plurality of DRAMs.
Claim 22
Dependent Claim
155 words
A computer system for minimizing power consumption in a video subsystem comprising: a CPU connected to a bus; a plurality of peripherals connected to said CPU by the bus; and a video subsystem connected to a video monitor and connected to said CPU by the bus, comprising: a frame buffer comprising dynamic memory; a clock circuit for generating a PCLK clock and a MCLK clock, and for disabling said PCLK clock and for decreasing a frequency of said MCLK clock in response to an inactivity signal; a RAMDAC, connected to said frame buffer and to said clock circuit, driven by said PCLK clock; and a video controller, driven by said MCLK clock, for programmably controlling a dynamic memory refresh rate of said frame buffer and for increasing the dynamic memory refresh rate to offset a decrease in the frequency of said MCLK clock in order to maintain the normal refresh rate of the dynamic memory.
Claim 23
Dependent Claim
155 words
A computer system for minimizing power consumption in a video subsystem comprising: a CPU connected to a bus; a plurality of peripherals connected to said CPU by the bus; and a video subsystem connected to a video monitor and connected to said CPU by the bus, comprising: a frame buffer comprising dynamic memory; a clock circuit for generating a PCLK clock and a MCLK clock, and for disabling said PCLK clock and for decreasing a frequency of said MCLK clock in response to an inactivity signal; a RAMDAC, connected to said frame buffer and to said clock circuit, driven by said PCLK clock; and a video controller, driven by said MCLK clock, for programmably controlling a dynamic memory refresh rate of said frame buffer and for increasing the dynamic memory refresh rate to offset a decrease in the frequency of said MCLK clock in order to maintain the normal refresh rate of the dynamic memory.
Claim 24
Dependent Claim
26 words
The computer system of claim 19 wherein said video controller further comprises power management circuitry comprising a plurality of configuration registers for controlling the clock circuitry.
Claim 25
Dependent Claim
38 words
The system of claim 19 wherein said clock circuitry further comprises at least one PCLK register for controlling the frequency of the first clock and at least one MCLK register for controlling the frequency of the second clock.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-04 | 1999-12-04 | 2000-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-04 | 2003-12-04 | 2004-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-04 | 2007-12-04 | 2008-06-04 | $7700.00 | Window Closed / Lapsed |