Patent US5524211A successfully refreshed from Google Patents.
US5524211A
Expired / Lapsed
US
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System for employing select, pause, and identification registers to control communication among plural processors
Assignee: Hewlett Packard Development Co LP
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Filing: 1993-03-25
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Granted: 1996-06-04
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Expires: 2013-03-25
Abstract
Abstract A control unit is assigned to each microprocessor of a multiprocessor (MP) system. Each control unit is in communication with its associated microprocessor and the system bus. Each control unit comprises a register set having bit registers and word registers. Messages can be sent to one or more of the microprocessors concurrently via a select function. Specifically, a data byte is bit sliced or bit masked so that the select register associated with one or more processors is activated. The bit registers which are activated, enable associated word registers for subsequent accesses. Consequently, one or more processors may be accessed concurrently. Moreover, bit pause registers are utilized so as to simultaneously pause one or more processors. Finally, bit identification registers may be read by any processor to determine the location of the processor.
Inventors
- 👤 Greg Woods
- 👤 Carol Bassett
- 👤 Robert Campbell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:04
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/177
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
200 words
A multiprocessing computer which includes a plurality of processing entities connected together by a system bus, the processing entities utilizing the system bus to transfer data, each processing entity comprising: (a) a processor; (b) a select register coupled to the system bus, the select register storing a first data bit pertaining exclusively to the processor, the select register receiving the first data bit from a first bit position of a first data transfer unit sent on the system bus, the first bit position being unique to the processing entity; (c) a word register connected to the system bus and the processor, the word register storing transferred data directed to the processor, the word register receiving the transferred data from the system bus and the transferred data being available to the processor after being received by the word register; and, (d) decode logic means, coupled to the system bus, the select register and the word register, for controlling the word register, the decode logic means accessing the first data bit within the select register and enabling and disabling the word register in accordance with the first data bit, thereby permitting selective control of communication to the processor via the system bus.
Claim 2
Dependent Claim
200 words
A multiprocessing computer which includes a plurality of processing entities connected together by a system bus, the processing entities utilizing the system bus to transfer data, each processing entity comprising: (a) a processor; (b) a select register coupled to the system bus, the select register storing a first data bit pertaining exclusively to the processor, the select register receiving the first data bit from a first bit position of a first data transfer unit sent on the system bus, the first bit position being unique to the processing entity; (c) a word register connected to the system bus and the processor, the word register storing transferred data directed to the processor, the word register receiving the transferred data from the system bus and the transferred data being available to the processor after being received by the word register; and, (d) decode logic means, coupled to the system bus, the select register and the word register, for controlling the word register, the decode logic means accessing the first data bit within the select register and enabling and disabling the word register in accordance with the first data bit, thereby permitting selective control of communication to the processor via the system bus.
Claim 3
Dependent Claim
105 words
A multiprocessing computer as in claim 1 wherein each processing entity additionally comprises: a pause register, coupled to the system bus and the decode logic means, the pause register receiving a second data bit pertaining exclusively to the processor, the pause register receiving the second data bit from the first bit position of a second data transfer unit sent on the system bus, wherein the decode logic means accesses the second data bit within the pause register and enables and disables the processor based upon the second data bit accessed from the pause register, thereby permitting selective disabling of the processor via the system bus.
Claim 4
Dependent Claim
108 words
A multiprocessing computer as in claim 1 wherein each processing entity generates and sends network messages and each processing entity additionally comprises: an identification register, coupled to the system bus and the decode logic means, the identification register containing a second data bit pertaining exclusively to the processor, wherein when the processing entity generates a first network message, the decode logic means sets the second data bit to a first logic value and when the processing entity sends the first network message, the decode logic means places contents of the identification register in a second data transfer unit of the first network message at the first bit position.
Claim 5
Dependent Claim
141 words
A multiprocessing computer which includes a plurality of processing entities connected together by a system bus, the processing entities utilizing the system bus to transfer data, each processing entity comprising: (a) a processor; (b) a pause register coupled to the system bus, the pause register storing a first data bit pertaining exclusively to the processor, the pause register receiving the first data bit from a first bit position of a first data transfer unit sent on the system bus, the first bit position being unique to the processing entity; and (c) decode logic means, coupled to the system bus and the pause register, for accessing the first data bit within the pause register and enabling and disabling the processor based upon the first data bit accessed from the pause register, thereby permitting selective disabling of the processor via the system bus.
Claim 6
Dependent Claim
141 words
A multiprocessing computer which includes a plurality of processing entities connected together by a system bus, the processing entities utilizing the system bus to transfer data, each processing entity comprising: (a) a processor; (b) a pause register coupled to the system bus, the pause register storing a first data bit pertaining exclusively to the processor, the pause register receiving the first data bit from a first bit position of a first data transfer unit sent on the system bus, the first bit position being unique to the processing entity; and (c) decode logic means, coupled to the system bus and the pause register, for accessing the first data bit within the pause register and enabling and disabling the processor based upon the first data bit accessed from the pause register, thereby permitting selective disabling of the processor via the system bus.
Claim 7
Independent Claim
153 words
A system in each processing entity of a multiprocessing computer for permitting a process within the processing entity to discover an address of the processing entity within the multiprocessing computer, the multiprocessing computer including a system bus connected to each processing entity, each processing entity generating and sending network messages over the system bus, the system comprising: (a) a processor; (b) an identification register coupled to the system bus, the identification register storing a first data bit pertaining exclusively to the processor; and, (c) decode logic means, coupled to the system bus and the identification register, for setting the first data bit to a first logic value when the processing entity generates a first network message, and for placing contents of the identification register in a data transfer unit of the first network message when the processing entity sends the first network message, the first bit position being unique to the processing entity.
Claim 8
Independent Claim
153 words
A system in each processing entity of a multiprocessing computer for permitting a process within the processing entity to discover an address of the processing entity within the multiprocessing computer, the multiprocessing computer including a system bus connected to each processing entity, each processing entity generating and sending network messages over the system bus, the system comprising: (a) a processor; (b) an identification register coupled to the system bus, the identification register storing a first data bit pertaining exclusively to the processor; and, (c) decode logic means, coupled to the system bus and the identification register, for setting the first data bit to a first logic value when the processing entity generates a first network message, and for placing contents of the identification register in a data transfer unit of the first network message when the processing entity sends the first network message, the first bit position being unique to the processing entity.
Claim 9
Dependent Claim
47 words
The system of claim 5, wherein the processor generates bus request signals to be sent over the system bus and wherein the decode logic means monitors the bus request signals from the processor to determine when to set the first data bit to the first logic value.
Claim 10
Dependent Claim
46 words
The system of claim 5, wherein the processor generates bus acknowledge signals to be sent over the system bus and wherein the decode logic monitors the bus acknowledge signals from the processor to determine when to set the first data bit to the first logic value.
Claim 11
Dependent Claim
46 words
The system of claim 5, wherein the processor generates output enable signals to be sent over the system bus and wherein the decode logic monitors address output enable signals from the processor to determine when to set the first data bit to the first logic value.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-04 | 1999-12-04 | 2000-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-04 | 2003-12-04 | 2004-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-04 | 2007-12-04 | 2008-06-04 | $7700.00 | Window Closed / Lapsed |