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US5524209A
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System and method for controlling the competition between processors, in an at-compatible multiprocessor array, to initialize a test sequence
Assignee: Unisys Corp
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Filing: 1995-02-27
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Granted: 1996-06-04
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Expires: 2015-02-27
Abstract
Abstract A multiprocessor array where any single multiprocessor can be needed to execute a prescribed sequence and more than one of the processors may compete to initialize this sequence, and wherein a "semaphore port" SP is coupled to all processors, this port SP being adapted to normally signal "GO", but after "first-access" by a said processor, which thus becomes a "selected processor", to thereupon signal "STOP" to all other, "non-selected", processors, and so deny access until a given test sequence is completed.
Inventors
- 👤 Robert F. Parker
- 👤 Anil K. Gupta
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:33
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
152 words
In an AT-compatible multiprocessor array where any one processor can be needed to execute a prescribed test sequence and more than one of the processors may compete to initialize this sequence, a method of controlling this competition comprising the steps of: coupling a special I/O "semaphore port" SP to all processors; adapting this port to normally signal "GO", but after a "first-access" by a said processor, which thus becomes a "selected processor", to thereupon signal "STOP" to all other "non-selected" processors, and so deny access until the prescribed subject test sequence is completed; and also coupling "other-reset" OR means to all said processors while arranging such means OR to allow a so-selected processor to reset the other processors; said OR means being arranged to comprise an "other-processor-reset" port OPR, which, in turn, is arranged to require three back-to-back I/O cycles to confirm "other-processor-reset" and so avoid accidental reset of any non-selected processor.
Claim 2
Dependent Claim
152 words
In an AT-compatible multiprocessor array where any one processor can be needed to execute a prescribed test sequence and more than one of the processors may compete to initialize this sequence, a method of controlling this competition comprising the steps of: coupling a special I/O "semaphore port" SP to all processors; adapting this port to normally signal "GO", but after a "first-access" by a said processor, which thus becomes a "selected processor", to thereupon signal "STOP" to all other "non-selected" processors, and so deny access until the prescribed subject test sequence is completed; and also coupling "other-reset" OR means to all said processors while arranging such means OR to allow a so-selected processor to reset the other processors; said OR means being arranged to comprise an "other-processor-reset" port OPR, which, in turn, is arranged to require three back-to-back I/O cycles to confirm "other-processor-reset" and so avoid accidental reset of any non-selected processor.
Claim 3
Dependent Claim
16 words
The method of claim 1, wherein said cycles comprise: READ-WRITE-READ uninterrupted by any other I/O cycle.
Claim 4
Dependent Claim
15 words
The method of claim 2, wherein said READ-WRITE-READ sequence is repeated until "reset-other" is confirmed.
Claim 5
Dependent Claim
136 words
An AT-compatible multiprocessor array where any single multiprocessor can be needed to execute a prescribed sequence and more than one of the processors may compete to initialize this sequence, wherein a special I/O "semaphore port" SP is coupled to all processors, this port SP being adapted to normally signal "GO", but after a "first-access" by a said processor, which thus becomes a"selected processor", to thereupon signal "STOP" to all other, "non-selected", processors, and so deny access until a given test sequence is completed; and wherein a "other-reset" OR means is also coupled to all said processors and is adapted to allow a so-selected processor to reset the other processors; said "other-reset" OR means comprising an "other-processor-reset" port OPR, which requires three back-to-back I/O cycles to confirm "other-processor-reset" to so avoid accidental reset of any non-selected processor.
Claim 6
Dependent Claim
136 words
An AT-compatible multiprocessor array where any single multiprocessor can be needed to execute a prescribed sequence and more than one of the processors may compete to initialize this sequence, wherein a special I/O "semaphore port" SP is coupled to all processors, this port SP being adapted to normally signal "GO", but after a "first-access" by a said processor, which thus becomes a"selected processor", to thereupon signal "STOP" to all other, "non-selected", processors, and so deny access until a given test sequence is completed; and wherein a "other-reset" OR means is also coupled to all said processors and is adapted to allow a so-selected processor to reset the other processors; said "other-reset" OR means comprising an "other-processor-reset" port OPR, which requires three back-to-back I/O cycles to confirm "other-processor-reset" to so avoid accidental reset of any non-selected processor.
Claim 7
Dependent Claim
16 words
The array of claim 4, wherein said cycles comprise: READ-WRITE-READ uninterrupted by any other I/O cycle.
Claim 8
Dependent Claim
15 words
The array of claim 5, wherein said READ-WRITE-READ sequence is repeated until "reset-other" is confirmed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-04 | 1999-12-04 | 2000-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-04 | 2003-12-04 | 2004-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-04 | 2007-12-04 | 2008-06-04 | $7700.00 | Window Closed / Lapsed |